The CHERI capability model: Revisiting RISC in an age of risk (ISCA 2014) 2014-07-03 Academic papers, Open-source security, Operating systems, Processors, Programmable logicRobert N. M. Watson Last week, Jonathan Woodruff presented our joint paper on the CHERI memory model, The CHERI capability model: Revisiting RISC in an age of risk, at the 2014 International Symposium on Computer Architecture (ISCA) in Minneapolis (video, slides). This is our first full paper on Capability Hardware Enhanced RISC Instructions (CHERI), collaborative work between Simon Moore’s and my team composed of members of the Security, Computer Architecture, and Systems Research Groups at the University of Cambridge...