Posted on 03/12/2013 2:37:20 PM PDT by Ernest_at_the_Beach
Photo: Calxeda
There are two giants in the computer processor industry. One is Intel, which builds most of the processors in today’s PCs and servers. The other is ARM Holdings, in Cambridge, England, which thanks to its vast ecosystem of partners has established near-complete dominance of the market for the core logic inside smartphones and tablets.
But the demand for energy-efficient chips is reshaping the industry. As the PC market flattens, Intel aims to capture a sizable chunk of the rapidly growing mobile market, which rose to nearly half a billion smartphones in 2011. And chip designers in ARM’s camp are eyeing a US $50 billion server market, fueled by the rise of social networking and cloud computing.
The coming months will see a number of volleys exchanged across the line that has traditionally divided the high-performance and low-power chip markets. One of the first will come from a small start-up in Austin, Texas, called Calxeda (pronounced cal-ZAY-dah). The fabless firm will begin shipping chips for servers based on 32-bit ARM mobile processor designs. They’ll soon be joined by AppliedMicro, in Sunnyvale, Calif., which is working on an even speedier, 64-bit ARM-based chip. At the same time, Intel will leap into the mobile game; two big companies—Lenovo and Motorola—plan to release phones based on Intel’s low-power Atom processor by the end of this year. (The very first Intel-based smartphone was launched in April by the India-based firm Lava International.)
Exactly how this competition shapes up will depend not on performance or power consumption but on the ratio between the two: performance per watt. And that metric is fueling a fiery debate over the fundamental differences between Intel’s x86 chips and ARM’s processors.
But the most obvious difference between the two may not actually be the important one, according to experts. ARM processors use reduced instruction set computing (RISC), while x86 processors rely on an older approach, retroactively dubbed complex instruction set computing (CISC).
Both RISC and CISC architectures govern the set of machine-level instructions, compiled from more complex code, that a chip can execute. CISC chips have a wider vocabulary—they can perform certain operations in one step that might require a series of commands on a RISC chip. But RISC chips can better handle speed-boosting tricks like allowing overlapping operations during each clock cycle.
As a result, over the years, Intel has incorporated decoders into its x86 chips to convert CISC instructions to RISC instructions to boost performance. This conversion process takes energy, but it’s unclear whether this added step gives ARM an advantage when it comes to efficiency.
Instead, other differences between ARM and Intel chips may have more of a bearing on the coming competition. One key difference is microarchitecture—the particular way that processor resources such as cache and registers are distributed and instructions are scheduled. Today’s high-performance processors, for example, are designed so instructions can be performed out of order. Every part of a computation is done as soon as possible to boost speed. Chips that employ this approach have built-in bookkeeping to make sure that the results are assembled in the right order at the end of the process.
Such tricks can have a big impact on efficiency and performance, says Benjamin C. Lee, an assistant professor of electrical and computer engineering at Duke University, in Durham, N.C. While a researcher at Microsoft, Lee studied how well the company’s Bing Web search engine performed on Intel’s out-of-order Xeon server chip and its in-order Atom netbook processor. Each core on the Atom chip could handle queries at half the rate of a Xeon chip core but required just 20 percent of the energy per request. However, Atom wasn’t able to handle some of the more complex requests.
Microarchitecture will be a key battleground in any competition between Intel and ARM chips, says microprocessor industry analyst Linley Gwennap. Eking out even a slight improvement in performance can come at the expense of a large boost in power consumption. If ARM-based devices like AppliedMicro’s 64-bit server chip are to compete with Intel chips in the server market, developers will have to accept similar diminishing returns, he says.
Somewhere I think I posted about Hp using the Calxeda stuff.
I’m still in the dark on why they started with 32-bit architecture vs. the much more expansive 64-bit? I’d imagine they have to start somewhere, and in reality, since the ARM processor is performing both storage and processing, I suppose the “4 GB memory limit” isn’t an issue if each MP is performing independent of any cache or pre-processing architecture.
However, the discussion of RISC vs. CISC wouldn’t even exist in 64-bit architecture, as they could store the complex instruction sets redundant to the reduced or as a supplement thereof, at least if I’m understanding the two properly.
With the shrinking size of components, it’s only a matter of time before hundreds of 1RU (Rack Unit) servers (i.e. ProLiant-class DL360s) can be crunched into a single device. We already know existing smartphones and tablets are hundreds of times more powerful than what was used on the lunar landers, and that was just 50 years ago. Imagine how insane it’s going to be in the next 50?
An over simplified answer is complexity = cost.
Also, based on a lot of software product development performance testing in a hosted environment, 32 bit architectures handle instruction execution faster than 64 bit per clock cycle.
Of course, there are a wide array of variables - like the compiler's effectiveness in optimizing high level code down to machine code, data size and memory access needs, L1 and L2 cache, etc.
One thing that's different is instruction-alignments; on a MIPS (some would call that the defining RISC, but ARM is pretty similar) all instructions are on a particular alignment, on the x86 architecture this is not true because the 'switch' for extended operations is simply prefixing some special value to the instruction -- while this seems like it shouldn't matter, there is one very important conclusion: given some values at a particular address you cannot tell if it is a valid operation in x86 whereas you can with the MIPS (if that address is properly aligns [i.e. ADDRESS mod 4 = 0, IIRC]).
From this conclusion there are consequences, explored in this paper which proves it impossible to secure the x86 system from malicious attack using this feature of x86 -- the same attack is very [VERY] difficult with a MIPS instruction-set, and indeed could be completely secured, with the addition of a LAND instruction, as outlined here.
(Yes, I realize there are other CISCs out there than x86, and other RISCs than MIPS [or ARM].)
Intel has a lot to worry about, but the same can be said of its competitors.
Thanks Ernest.
Actually I don’t think ARM had their 64 bit circuitry ready yet.....when Calxeda started.
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hella cool graphic Martin
I saw the comment and knew the poster was a local even before I looked...
‘hella’ being the tip-off. :)
I picked that up when I lived out there for years. Now I mix ‘wicked’ and ‘hella’ fairly often in my vernacular diction and people look at me with a serious jaundiced eye.
Man,...guess I got busy and never got back to this thread....LOL!
When Calxeda started the design of their board, there wasn't a 64 bit ARM core available. (Note that the article is over a year old, and speaks of Calxeda technology developed a year or two before that).
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