I’m still in the dark on why they started with 32-bit architecture vs. the much more expansive 64-bit? I’d imagine they have to start somewhere, and in reality, since the ARM processor is performing both storage and processing, I suppose the “4 GB memory limit” isn’t an issue if each MP is performing independent of any cache or pre-processing architecture.
However, the discussion of RISC vs. CISC wouldn’t even exist in 64-bit architecture, as they could store the complex instruction sets redundant to the reduced or as a supplement thereof, at least if I’m understanding the two properly.
With the shrinking size of components, it’s only a matter of time before hundreds of 1RU (Rack Unit) servers (i.e. ProLiant-class DL360s) can be crunched into a single device. We already know existing smartphones and tablets are hundreds of times more powerful than what was used on the lunar landers, and that was just 50 years ago. Imagine how insane it’s going to be in the next 50?
An over simplified answer is complexity = cost.
Also, based on a lot of software product development performance testing in a hosted environment, 32 bit architectures handle instruction execution faster than 64 bit per clock cycle.
Of course, there are a wide array of variables - like the compiler's effectiveness in optimizing high level code down to machine code, data size and memory access needs, L1 and L2 cache, etc.
One thing that's different is instruction-alignments; on a MIPS (some would call that the defining RISC, but ARM is pretty similar) all instructions are on a particular alignment, on the x86 architecture this is not true because the 'switch' for extended operations is simply prefixing some special value to the instruction -- while this seems like it shouldn't matter, there is one very important conclusion: given some values at a particular address you cannot tell if it is a valid operation in x86 whereas you can with the MIPS (if that address is properly aligns [i.e. ADDRESS mod 4 = 0, IIRC]).
From this conclusion there are consequences, explored in this paper which proves it impossible to secure the x86 system from malicious attack using this feature of x86 -- the same attack is very [VERY] difficult with a MIPS instruction-set, and indeed could be completely secured, with the addition of a LAND instruction, as outlined here.
(Yes, I realize there are other CISCs out there than x86, and other RISCs than MIPS [or ARM].)
Actually I don’t think ARM had their 64 bit circuitry ready yet.....when Calxeda started.
When Calxeda started the design of their board, there wasn't a 64 bit ARM core available. (Note that the article is over a year old, and speaks of Calxeda technology developed a year or two before that).