Somewhere I think I posted about Hp using the Calxeda stuff.
I’m still in the dark on why they started with 32-bit architecture vs. the much more expansive 64-bit? I’d imagine they have to start somewhere, and in reality, since the ARM processor is performing both storage and processing, I suppose the “4 GB memory limit” isn’t an issue if each MP is performing independent of any cache or pre-processing architecture.
However, the discussion of RISC vs. CISC wouldn’t even exist in 64-bit architecture, as they could store the complex instruction sets redundant to the reduced or as a supplement thereof, at least if I’m understanding the two properly.
With the shrinking size of components, it’s only a matter of time before hundreds of 1RU (Rack Unit) servers (i.e. ProLiant-class DL360s) can be crunched into a single device. We already know existing smartphones and tablets are hundreds of times more powerful than what was used on the lunar landers, and that was just 50 years ago. Imagine how insane it’s going to be in the next 50?