Could RISC-V become a force in high performance computing?

The Register ^

[BereanBrain]

Yes.

[Red Badger]

Self programming computers?.......................

[LesbianThespianGymnasticMidget]

Concur. Yes.

[Yo-Yo]

OK, RISC is Reduced Instruction Set Computer. What does the V signify?

[SuperLuminal]

I’m OK with it as long as I can still run my DOS OS machines...

[Renfrew]

“When in 1993, the TOP500 list came out, there was only one Linux system on it. Nowadays, all the systems on the TOP500 list run Linux.”

I didn’t know this. It’s very interesting. If you are building a specialized computer it makes sense that need a lot of customization on your OS. Easy to do with Linux.

[dadfly]

bookmark.

[MAAG]

What does the V signify?

5

[Joe Brower]

RISC-V

[Paal Gulli]

I’ve still got a couple of risc pizza boxes stashed away somewhere. I probably should give them to a museum. Or turn them into planters.

My how the mighty have fallen.

[FarCenter]

“V” is “Five”.

https://en.wikipedia.org/wiki/RISC-V

David Patterson at Berkeley joined the collaboration as he was the originator of the Berkeley RISC,[16] and the RISC-V is the eponymous fifth generation of his long series of cooperative RISC-based research projects.

[FrankRizzo890]

I used to work for Intel. I have lots of friends who still DO, and I can tell you the general thought is that RISC-V is going to take over the CPU market wiping out Intel, AMD, and ARM in the process.

[Yo-Yo]

Thank you all. I skimmed the Wikipedia article before posting, but I didn't see the reference that FarCenter quoted about David Patterson and the fifth generation of RISC architecture.

I also couldn't find any reference to RISC-II, RISC-III, or RISC-IV, so I didn't know if it was a generation designation or something else.

Thanks again, all.

[steve86]

The instruction set is a reasonably simple MIPS architecture-like traditional RISC using a 3-operand load-store architecture, with 16 or 32 general-purpose registers and a fixed 32-bit instruction length. The instruction set is mostly identical between the 32- and 64-bit versions of the specification, the main difference being the register width (32 or 64 bits) and page table layout. The OpenRISC specification includes all features common to modern desktop and server processors: a supervisor mode and virtual memory system, optional read, write, and execute control for memory pages, and instructions for synchronizing and interrupt handling between multiple processors. Another notable feature is a rich set of single instruction, multiple data (SIMD) instructions intended for digital signal processing.

--wikipedia

[FarCenter]

Mid second paragraph in “History” section.

Control-f and type Patterson.

[dinodino]

Yes, definitely.

[billakay]

Interestingly, with the introduction of powerful Apple (ARM) workstations, UNIX on RISC has risen again!

[Dr. Sivana]

RISC-V is going to take over the CPU market wiping out Intel, AMD, and ARM in the process.

ARM (and Apple's M-series) are RISC chips, so are IBM's PowerPC chips. Intel's and AMD's offerings have gotten less "CISCey" over the years. The ARM offerings at least should be rather easy to render RISC-V compliant.

Intel will still have a place with chiosets and their own version of RISC-V. AMD will still have graphics chips. All of them will have patentable offerings for things like low-power, low-heat, maximum cores, etc. There will also be a place for transmeta type translators to support legacy systems and software.

[taxcontrol]

I have always thought that a RISC-V cpu could be augmented with a FPGA inside the OS if the pipelining could recognize a repeated series of calls, they could be implemented into the FPGA to create a path that would be faster than individual execution. Kind of CISC on the fly.

The historical down side is the amount of time that it takes to reprogram the FPGA.