Posted on 02/08/2023 12:08:26 PM PST by FarCenter
The RISC-V architecture looks set to become more prevalent in the high performance computing (HPC) sector, and could even become the dominant architecture, at least according to some technical experts in the field.
Meanwhile, the European High Performance Computing Joint Undertaking (EuroHPC JU) has just announced a project aimed at the development of HPC hardware and software based on RISC-V, with plans to deploy future exascale and post-exascale supercomputers based on this technology.
RISC-V has been around for at least a decade as an open source instruction set architecture (ISA), while actual silicon implementations of the ISA have been coming to market over the past several years.
Among the attractions of this approach are that the architecture is not only free to use, but can also be extended, meaning that application-specific functions can be added to a RISC-V CPU design, and accessed by adding custom instructions to the standard RISC-V set.
This latter could prove to be a driving factor for broader adoption of RISC-V in the HPC sector, according to Aaron Potler, Distinguished Engineer at Dell Technologies.
“There's synergy and growing strength in the RISC-V community in HPC,” Potler said, “and so RISC-V really does have a very, very good chance to become more prevalent on HPC.”
Potler was speaking in a Dell HPC Community online event, outlining perspectives from Dell’s Office of the Chief Technology and Innovation Officer.
However, he conceded that to date, RISC-V has not really made much of a mark in the HPC sector, largely because it wasn't initially designed with that purpose in mind, but that there is “some targeting now to HPC” because of the business model it represents.
He made a comparison of sorts with Linux, which like RISC-V, started off as a small project, but which grew and grew in popularity because of its open nature (it was also free to download and run, as Potler acknowledged).
“Nobody would have thought then that Linux would run on some high end computer. When in 1993, the TOP500 list came out, there was only one Linux system on it. Nowadays, all the systems on the TOP500 list run Linux. Every single one of them. It's been that way for a few years now,” he said.
If Linux wasn’t initially targeting the HPC market, but was adopted for it because of its inherent advantages, perhaps the same could happen with RISC-V, if there are enough advantages, such as it being an open standard.
Yes.
Self programming computers?.......................
Concur. Yes.
OK, RISC is Reduced Instruction Set Computer. What does the V signify?
I’m OK with it as long as I can still run my DOS OS machines...
“When in 1993, the TOP500 list came out, there was only one Linux system on it. Nowadays, all the systems on the TOP500 list run Linux.”
I didn’t know this. It’s very interesting. If you are building a specialized computer it makes sense that need a lot of customization on your OS. Easy to do with Linux.
bookmark.
5
I’ve still got a couple of risc pizza boxes stashed away somewhere. I probably should give them to a museum. Or turn them into planters.
My how the mighty have fallen.
“V” is “Five”.
https://en.wikipedia.org/wiki/RISC-V
David Patterson at Berkeley joined the collaboration as he was the originator of the Berkeley RISC,[16] and the RISC-V is the eponymous fifth generation of his long series of cooperative RISC-based research projects.
I used to work for Intel. I have lots of friends who still DO, and I can tell you the general thought is that RISC-V is going to take over the CPU market wiping out Intel, AMD, and ARM in the process.
I also couldn't find any reference to RISC-II, RISC-III, or RISC-IV, so I didn't know if it was a generation designation or something else.
Thanks again, all.
The instruction set is a reasonably simple MIPS architecture-like traditional RISC using a 3-operand load-store architecture, with 16 or 32 general-purpose registers and a fixed 32-bit instruction length. The instruction set is mostly identical between the 32- and 64-bit versions of the specification, the main difference being the register width (32 or 64 bits) and page table layout. The OpenRISC specification includes all features common to modern desktop and server processors: a supervisor mode and virtual memory system, optional read, write, and execute control for memory pages, and instructions for synchronizing and interrupt handling between multiple processors. Another notable feature is a rich set of single instruction, multiple data (SIMD) instructions intended for digital signal processing.
--wikipedia
Mid second paragraph in “History” section.
Control-f and type Patterson.
Yes, definitely.
Interestingly, with the introduction of powerful Apple (ARM) workstations, UNIX on RISC has risen again!
I have always thought that a RISC-V cpu could be augmented with a FPGA inside the OS if the pipelining could recognize a repeated series of calls, they could be implemented into the FPGA to create a path that would be faster than individual execution. Kind of CISC on the fly.
The historical down side is the amount of time that it takes to reprogram the FPGA.
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