Google is using AI to design chips that will accelerate AI

A new reinforcement-learning algorithm has learned to optimize the placement of components on a computer chip to make it more efficient and less power-hungry.

3D Tetris: Chip placement, also known as chip floor planning, is a complex three-dimensional design problem. It requires the careful configuration of hundreds, sometimes thousands, of components across multiple layers in a constrained area. Traditionally, engineers will manually design configurations that minimize the amount of wire used between components as a proxy for efficiency. They then use electronic design automation software to simulate and verify their performance, which can take up to 30 hours for a single floor plan.

Time lag: Because of the time investment put into each chip design, chips are traditionally supposed to last between two and five years. But as machine-learning algorithms have rapidly advanced, the need for new chip architectures has also accelerated. In recent years, several algorithms for optimizing chip floor planning have sought to speed up the design process, but they’ve been limited in their ability to optimize across multiple goals, including the chip’s power draw, computational performance, and area.

Intelligent design: In response to these challenges, Google researchers Anna Goldie and Azalia Mirhoseini took a new approach: reinforcement learning. Reinforcement-learning algorithms use positive and negative feedback to learn complicated tasks. So the researchers designed what’s known as a “reward function” to punish and reward the algorithm according to the performance of its designs. The algorithm then produced tens to hundreds of thousands of new designs, each within a fraction of a second, and evaluated them using the reward function. Over time, it converged on a final strategy for placing chip components in an optimal way.

Validation: After checking the designs with the electronic design automation software, the researchers found that many of the algorithm’s floor plans performed better than those designed by human engineers. It also taught its human counterparts some new tricks, the researchers said.

This is 100% in my wheelhouse. LOTS and LOTS of design and Electronic Design Automation (EDA) companies are already using AI methods in their tools, where it makes sense.

EDA companies typically are on the leading edge of any way to speed up execution or improve quality of results, there’s a whole conference (DAC) dedicated for industry and academia to show off their latest research.

The need, and the trick, is to get ALL your components optimally placed and routed, as the design will only run as fast as your slowest path (for all paths on that clock). And to have it run in a reasonable amount of time, so you can turn around a logic update quickly.

I suspect that this is some OK research, paired with a huge PR budget. Google is a fairly new design house.

I worked with this guy, Robert Widlar and helped start National Semiconductor in the mid--60's.(I was an engineering technician)

Even then, I thought the things we were doing was unbelieveable.....it's been that way for me for 55 years now. I retired from TI at the end of 1994.

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