FPF 2005: P.A. Semi's PA6T-1682M System on a Chip

Real World Technologies ^ | 10-24-2005 | David Kanter

[Ernest_at_the_Beach]

Introduction

Recently, the computer industry has struggled with power consumption and heat dissipation. Part of this was because architects had assumed that system builders and consumers would be willing to deal with 100W chips, in order to have the highest performance. While the general purpose computation market has been heating up, the embedded market has always been far more conscious of cost, heat, power and space. At the 2005 Fall Processor Forum, P.A. Semi, a three year old start up has come out of the shadows to present a brand new system on a chip (SOC) architecture for high performance embedded designs.

P.A. Semi has an incredibly strong team of 150 engineers that have been joined from throughout the industry. Three of the P.A. executives are Dan Dobberpuhl, Jim Keller and Pete Bannon. Astute readers will notice that all three of these can trace their roots to the legendary design teams at the Digital Equipment Corporation and were heavily involved in VAX, Alpha and/or StrongARM design. P.A. Semi has also been able to reap the benefit of the high attrition among proprietary RISC design teams, picking up designers from Intel, AMD, Sun and SiByte.

While many expected that P.A. Semi would be using a MIPS core, based on their heritage from SiByte, P.A. Semi is a founding member of Power.org, and along with IBM and Motorola, is the third company with a Power architectural license. The only other options for the ISA were MIPS or ARM, and the rationale for using Power is relatively clear. While ARM is the dominant architecture in the PDA and cell phone (and iPod) markets, it has virtually no presence in telecommunications. MIPS still has a strong presence in telecommunications and other embedded markets, but unfortunately, lacks a heavyweight sponsor like IBM. IBM has invested a tremendous amount of time, money and effort promoting the Power architecture for a couple of reasons. First of all, they want to ensure that Power survives, unlike many proprietary RISC architectures, and widespread adoption is the best chance it has. Second, by encouraging fabless PowerPC based designs, IBM’s Micro-electric division can hopefully pick up some much needed business for their fabs. Ultimately, this means that there are more tools, support and developers for PowerPC than for the alternatives. This made P.A. Semi’s choice dead simple, take advantage of IBM and Motorola’s investments in infrastructure, but differentiate with a unique product family.

The PWRficient Family

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Conclusion

The architects at P.A. Semi have combined a very intelligent, reuse oriented design philosophy with a relentless pursuit of low power and high performance. While the chips have yet to hit the fab, the results look promising and the team involved certainly has a history of delivering in spades. The PA6T-1682M will likely prove to be an eminently capable embedded product including several innovative features, most notably, the reconfigurable I/O and offload engines. Just as interesting, if products in the PWRficient family can be rapidly deployed as hope, this could dramatically alter the return on investment equation for P.A. Perhaps best of all, this is yet another added element of diversity into what many industry observes thought was a relatively stable market.

[Ernest_at_the_Beach]

Another microprocessor , low power , impressive compute power, likely would run embedded Linux.

[Ernest_at_the_Beach]

Performance

Since the PA6T-1682M has yet to tape out, there are no hard performance numbers. However, P.A. Semi does have performance estimates based on extensive simulations. The results certainly look promising, with per core SPECint_2k estimated at 1100 and SPECFP_2k at 2255. In terms of more application specific performance, the whole chip can handle 10Gbps IPSec and SSL encryption, or 3,000 public key handshakes per second (using software). As a RAID 5 controller, it can sustain 2GB/s, which is enough to saturate around 26 hard drives. These numbers are extremely good for a chip that only dissipates around 13W, particularly the SPECFP_2k numbers. Unfortunately, since I am not a specialist in embedded systems, it is a bit hard for me to put these numbers in context. My overall assessment is that compared to other embedded systems, the PA6T-1682M will probably have superior performance, better compute density, extra features and certainly more flexible I/O.

Potential Applications

Just to whet the imagination of the audience, especially the high performance computing junkies, a potential HPC application was show and is reproduced in Figure 6 below.

Figure 6 – PWRficient based HPC System

The HPC system depicted features 8 cores, dissipating a total of around 50W from the CPUs and another 50W from the DRAM and I/O. The 8 cores would be capable of 128 SP GFLOP/s or 32 DP GFLOP/s. The system could use up to 128GB of memory spread across the 16 DDR2 controllers, and would provide 64GB/s of bandwidth. Of course, there are also the SERDES; up to 96, which would provide 240Gbps or 30GB/s of I/O bandwidth. These SERDES could be used for easy clustering, perhaps 10 Gigabit Ethernet between each MPU; if everything was kept on a single board, the latency should be quite low. The additional SERDES would likely be used for a communication backplane and for a storage array (perhaps controlled by a PA6T-1682M). Whether such a beast ever ships is highly speculative, but it is certainly an intriguing thought.

[RadioAstronomer]

Thanks for the post. Interesting. :-)

[Senator Bedfellow]

Since the PA6T-1682M has yet to tape out, there are no hard performance numbers.

What else matters, really? There's a long and sad history of chips that were world-beaters - on paper, anyway ;)