Since the PA6T-1682M has yet to tape out, there are no hard performance numbers. However, P.A. Semi does have performance estimates based on extensive simulations. The results certainly look promising, with per core SPECint_2k estimated at 1100 and SPECFP_2k at 2255. In terms of more application specific performance, the whole chip can handle 10Gbps IPSec and SSL encryption, or 3,000 public key handshakes per second (using software). As a RAID 5 controller, it can sustain 2GB/s, which is enough to saturate around 26 hard drives. These numbers are extremely good for a chip that only dissipates around 13W, particularly the SPECFP_2k numbers. Unfortunately, since I am not a specialist in embedded systems, it is a bit hard for me to put these numbers in context. My overall assessment is that compared to other embedded systems, the PA6T-1682M will probably have superior performance, better compute density, extra features and certainly more flexible I/O.
Potential Applications
Just to whet the imagination of the audience, especially the high performance computing junkies, a potential HPC application was show and is reproduced in Figure 6 below.
Figure 6 – PWRficient based HPC System
The HPC system depicted features 8 cores, dissipating a total of around 50W from the CPUs and another 50W from the DRAM and I/O. The 8 cores would be capable of 128 SP GFLOP/s or 32 DP GFLOP/s. The system could use up to 128GB of memory spread across the 16 DDR2 controllers, and would provide 64GB/s of bandwidth. Of course, there are also the SERDES; up to 96, which would provide 240Gbps or 30GB/s of I/O bandwidth. These SERDES could be used for easy clustering, perhaps 10 Gigabit Ethernet between each MPU; if everything was kept on a single board, the latency should be quite low. The additional SERDES would likely be used for a communication backplane and for a storage array (perhaps controlled by a PA6T-1682M). Whether such a beast ever ships is highly speculative, but it is certainly an intriguing thought.