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Intel: Where no chip has gone before
ZDNet News ^ | September 12, 2002, 11:50 AM PT | Michael Kanellos

Posted on 09/12/2002 11:05:43 PM PDT by Ernest_at_the_Beach


Hardware


Intel: Where no chip has gone before
By Michael Kanellos
Special to ZDNet News
September 12, 2002, 11:50 AM PT


TalkBack!


SAN JOSE, Calif.--The nanotechnology era is here, and Intel is looking at all the options.


News Focus
Intel Developer Forum news

On Thursday, at its Developer Forum here, The Santa Clara, Calif.-based chipmaker disclosed a number of technology changes and avenues of research that will direct the future development of its chips.

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The company, for instance, confirmed that it is working on a multiple-gate transistor, called the Tri-Gate transistor, that will, if eventually incorporated into commercially released chips, increase the amount of electricity, and hence the performance, of future transistors and microprocessors.

Intel also said that it is working with Harvard and other universities on silicon nanowires and carbon nanotubes, two experimental structures made up of, respectively, self-assembling silicon and carbon atoms. After 2010, one of these technologies could begin to replace standard transistors and over time become the building block of chips.

"Right now they both show promise. The determining factor will be to what degree they can be mass produced," said Sunlin Chou, Intel's senior vice president of technology and manufacturing. "The question is, can you make billions of these on a chip with consistent characteristics."

Thursday's keynote speeches, which also included a guest appearance by William Shatner, focused on the future of technology. In years to come, as chips continue to get less expensive, more powerful and smaller, computers and wireless connections will be embedded in everything. To prove the point, Intel's chief technical officer, Pat Gelsinger, opened the session decked out like a man who'd had a head-on collision with a Sharper Image catalogue. Riding a Segway scooter, Gelsinger was wearing a baseball hat with an eye monitor, a PDA with a camera, a Bluetooth headset, a universal remote control, and a vest with a server sewn in the back.

"When we get things to silicon, everything gets cheap. When it gets cheap, it gets ubiquitous," Gelsinger said.

So what does this mean on a practical level? By mid-decade, Intel will be able to integrate radios onto ordinary silicon chips, Gelsinger said. As a result, wireless communications will essentially become free. Optical products, which now require thousands of dollars and several engineers to tune, will become cheaper because many of the functions will be integrated into mass produce-able silicon chips.

It will also be easy to create sensor networks, where coin-sized motes spread over a large area can measure seismic activity, temperature, pressure and other factors. In an experiment at the Great Duck Island Environmental Preserve in Maine, researchers are using sensors to monitor how atmospheric changes can alter animal behavior. Now researchers have to make these observations directly, which can disturb animals.

As a part of such efforts, Intel on Thursday released TinyDB and TinyOS, a database and operating system for these sensors. The software is open source and uses little memory or energy.

Nano nano
While Gelsinger spoke of future applications, Chou focused on chip and transistor roadmaps, or release schedules. Nanotechnology, the science of manufacturing chips and other products with components measuring less than 100 nanometers (100 billionths of a meter) has already begun, he said. Transistor gates inside current chips measure 70 nanometers.

Next year, the nanotechnology era will begin in earnest with the release of 90-nanometer chips, Chou added. Manufacturing chips with smaller dimensions, however, will take quite a number of technological breakthroughs as time goes on.

For one thing, lithography, the science of printing circuit patterns onto chips, will have to change. Sometime in the decade, Extreme Ultraviolet (EUV) lithography will replace conventional lithography. The light wavelengths used in EUV measure only 13 nanometers compared with 193 nanometers for today's lithographic techniques.

"It will be possible to paint much finer lines in the future," Chou said. "We have gone beyond the technologically feasible phase and into the commercial development phase."

In a similar vein, Intel is experimenting with Atomic Layer Deposition, which lets manufacturers make chips by piling single layers of atoms on top of each other. "It relies on chemical properties to self-assemble," Chou said.

Transistors will also change. Starting with 90-nanometer manufacturing, chips will incorporate strained silicon, an extra layer of silicon and germanium atoms that improves performance. The germanium atoms spread out the silicon atoms and make it easier for electrons to travel. Executives at Amberwave, a leading strained silicon developer, liken it to running through a forest with fewer trees.

Later, layers of materials, such as high-k dielectrics, for preventing electron leakage will likely be incorporated. Further research, however, is required.

The Tri-Gate transistor is in a similar phase. Current transistors contain a single, horizontal gate. By contrast, the Tri-Gate rises up like a microscopic mesa, and allows electrons to flow on the horizontal top and the two vertical sides. The company has manufactured test transistors and will disclose further details at a conference next week in Japan, Chou said.

IBM and AMD are working on dual-gate transistors, both companies stated this week.

Nanotubes and/or nanowires will follow. "These new materials aren't going to come in and sweep away the silicon base. They will come in incrementally," Chou said.

Although Chou reiterated that it's way too early to tell which, if either, alternative will eventually be adopted, they are the two leading contenders. Carbon nanotubes are essentially hollow tubes that resemble a spool of chicken wire. Silicon nanowires, by contrast, are solid.

Shatner, meanwhile, discussed his new book, "I'm Working on That," about how different scientists such as Stephen Hawking have used science fiction to direct their research. Many of the examples in the book focus on ideas found in Star Trek that eventually became products. However, few, if any, of the concepts propounded in T.J. Hooker, his mid-80s cop show, are discussed in the book.

Gelsinger told Shatner that his favorite episode of Star Trek was "the one where you go back in time." Shatner's Capt. Kirk also apparently meets a woman and struggles with a decision, Gelsinger added.

"That's 17 episodes," Shatner replied.

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TOPICS: Business/Economy; Extended News; News/Current Events; Technical
KEYWORDS: computers; intel; techindex

1 posted on 09/12/2002 11:05:44 PM PDT by Ernest_at_the_Beach
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To: *tech_index; Mathlete; Apple Pan Dowdy; grundle; beckett; billorites; One More Time; ...
OFFICIAL BUMP(TOPIC)LIST
2 posted on 09/12/2002 11:06:41 PM PDT by Ernest_at_the_Beach
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To: Ernest_at_the_Beach
The company, for instance, confirmed that it is working on a multiple-gate transistor, called the Tri-Gate transistor, that will, if eventually incorporated into commercially released chips, increase the amount of electricity, and hence the performance, of future transistors and microprocessors.

What does "increase the amount of electricity" mean? Can someone give a better explanation of this?

3 posted on 09/13/2002 12:00:25 AM PDT by HAL9000
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To: Ernest_at_the_Beach
We shall be assimilated by the Borg.
4 posted on 09/13/2002 3:28:25 AM PDT by MedicalMess
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To: Ernest_at_the_Beach
Re #4

I guess people gave up on parallel CPU ideas for now. It used to be a craze. A single processor can be made faster everyday. But we seem to be still at a stage of one main CPU and multiple auxiliary processors at best.

5 posted on 09/13/2002 3:36:32 AM PDT by TigerLikesRooster
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To: HAL9000
It's a misprint. Should read decrease.....
6 posted on 09/13/2002 3:52:48 AM PDT by dennisw
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To: TigerLikesRooster
Multiple CPU's get a lot of discussion here

I want to build one!

7 posted on 09/13/2002 9:10:10 AM PDT by Ernest_at_the_Beach
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To: TigerLikesRooster
" I guess people gave up on parallel CPU ideas for now. It used to be a craze. A single processor can be made faster everyday. But we seem to be still at a stage of one main CPU and multiple auxiliary processors at best."

Virtually all mainframes have multiple processors today. Even the ones called uniprocessors, that use only a single processor for running the instruction stream, use an second one for internal housekeeping, and possibly to run the input/output subsystems as well. The problem is that almost all tasks are primarily sequential in nature. This means that, while steps 2 through 6 might not require earlier steps to be completed, 8 through 12 might depend on, for instance, one earlier step plus step 7.

Perhaps you could write a specialized program oriented around a specific application, that could be distributed among multiple processors that could make optimal use of resources. But this is a very difficult task, that generally must be designed in from the beginning. In fact, this subtasking is one of the strengths of IBM's operating system for large mainframes. Combined with the high-level compilers, communication, transaction, database, and file management subsystems, it parses out subtasks that can be assigned to other processors and brought back together to maintain logical flow.
8 posted on 09/13/2002 10:02:32 AM PDT by MainFrame65
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To: MainFrame65
Re #8

I am aware of that sequential bottleneck. You may know Amdhal's law which says that speed-up of factor more than 100 is not possible no matter how many processors you use. Many experimental parallel computers such as Connection Machine were said to run things only 30 times faster. Maybe IBM machine has more improved features.

It is a chicken-and-egg thing in some sense. Nobody wants to shift from current sequential programming practices because most computers are sequential. But As long as people practices sequential programming practices, parallel computers are of limited use.

Another problem is that true multiple CPU system can only run at its full potential when it is running asynchronous programs. Most of programs written today are not geared for asynchronous tasking. Too much sequential dependence. Let me know if IBM machine solved this problem in a satisfactory degree.

9 posted on 09/13/2002 9:16:26 PM PDT by TigerLikesRooster
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To: TigerLikesRooster
Mainframe clustering connects relatively small numbers of large, complex processors. Mostly these processors share a single pool of memory and all have access to all of the available I/O devices. Most processors - even medium-sized mainframes - use a single chip for each instruction processor, although the largest and fastest may have a more complex multichip architecture. One reason is that the chip architectures that allow the densest, most complex chips are not the fastest and most efficient circuits. One the most serious problems they face is heat dissipation. However, this is an area that is evolving rapidly, so that might have changed by now.

In fact, processors are improving rapidly, but RAM and disk memory are improving even faster in price and capacity, so optimal combinations are changing rapidly as well.

My handle tells you when I started repairing these things for IBM, so I have watched things change - a LOT! But one thing that has not changed is that people think sequentially, although their brains are the finest parallel processors in this corner of the galaxy. And people decide what they want their computers to do.

I would continue, but I have to leave for the local office IBM picnic, that we geezer retirees are allowed to attend in order to find out how far out of touch we are. Later.
10 posted on 09/14/2002 9:18:34 AM PDT by MainFrame65
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