Designers weigh in on the 6.25-Gbit/s move

EE Times ^ | October 7, 2002 | Stephan Ohr

[Ernest_at_the_Beach]

While "gigahertz processors" are using 400-MHz external clocks with internal multipliers to obtain 1.2- or 1.6-GHz clock rates, that doesn't mean system designers aren't experiencing problems with data pumping. Chip-to-chip memory transfers, clock trees and printed-circuit-board data paths, computer buses and backplanes are all packed with threats to signal integrity.

Each step of the way, the data communicated is threatened by noise, crosstalk and false triggers. While developers of optical-trunk lines will wring their hands over the technology hurdles associated with 40-Gbit/second transmission rates-not to mention the current shortage of investment capital-engineers are offering testimonials to the monumental task of getting 6.25 Gbits/s safely across 10 inches of copper.

Contributors to this week's In Focus section take on the high-speed data-transmission mission. All are experts in high-speed design and offer solutions that will make it happen: the bus topologies, memory interfaces and back-planes that are critical for pushing data to go, line by line, faster than 5 Gbits/s.

"As data rates move to 6.25 Gbits/s and beyond, backplane design becomes an increasingly intricate undertaking," contributors Gautam Patel of Teradyne and Bill Beale of Accelerant Networks write. "The interactions among every element-the on-chip interconnects, connectors, dielectric material and vias-must be taken into account." In their article, they detail a backplane that uses a buried microstrip and specialized connectors. Developments on this technology were also described at DesignCon, and the ability to reproduce data at these speeds is no mean feat.

A major tenet of the Teradyne-Accelerant contribution is that it's impossible to obtain gigabit data rates by simply compiling a system with high-speed components (semiconductor driver-receivers, connectors and backplane interconnects). The backplane must be understood as a total system: The interaction of a high-speed semiconductor transceiver with a high-speed interconnect does not automatically result in a high-speed system. This is a sentiment echoed by John D'Ambrosia of Tyco Electronics.

In an exclusive online contribution, D'Ambrosia suggests that the trend toward faster speeds over longer distances comes only from pairing interconnect components with matching semiconductors-a concept Tyco calls "active interconnects."

One way to make the signals that symbolize data come across faster is to lower the voltage swings between logic levels (data high and data low). But this technique runs the risk of sinking the signal, making it indistinguishable from its ambient noise.

A common solution, to which practically all the contributors point, is differential signaling-two lines per data bit, with data distinguished by differences in voltage levels on each line.

Memory maker Rambus Inc., it turns out, is embracing differential signaling in its next-generation processor-memory interface, called Yellowstone, according to contributor Richard Warmke, manager of the company's special-products division. Signaling goes up or down plus/minus 200 mV at about a 1-volt reference level-that is, 100 mV up or 100 mV down, Warmke writes in his contribution.

Meanwhile, senior design engineer Gary Henrickson of Analog Devices Inc. is using a popular differential-signal pattern, LVDS, to pull data from the company's high-speed (70-MHz) A/D converters.

Exclusive online articles include a piece by Ian Chen, chief technology officer, and Martin H. Eastburn, senior applications manager, at Cypress Semiconductor Corp. They see differential signaling as one means of minimizing the jitter that ordinarily accumulates between high-speed clock buffers.

Michael Fowler, principal product strategist at Fairchild Semiconductor, offers an interesting tutorial on backplane topologies. Though the fastest ones increasingly reflect differential-signaling techniques, the star, mesh and point-to-point backplanes offer other alternatives for moving data from card to card-or from one card to several receivers. Understand those topologies before going fast, Fowler warns.

A step-by-step approach to high-speed system design, with important recommendations on backplane and cable interfaces, is provided by Clark Kinnaird, applications manager of high-performance products at Texas Instruments. He recommends matching applications to interface standards and provides a detailed comparison table for data communications topologies and speeds.

And CAE applications engineer Michael Dzado of Zuken Inc. provides a nice walk-through on the process of simulating the behavior of a driver-receiver pair on a complex clock tree. The Zuken simulator relies on Ibis models of advanced CMOS logic.