Chinese Technicians Boldly Tried to Reverse Engineer ASML’s DUV Machines; Only to Break Them & Call the Dutch Firm For Help

The Chinese semiconductor industry faces a critical barrier in scaling up chip production, primarily due to the lack of lithography equipment in fabs. This limitation has confined firms like SMIC to a specific production volume and prevented them from scaling up significantly for several years now. Apart from developing in-house alternatives, it seems like Chinese engineers were actually keen to 'reverse engineer' ASML's DUV equipment, according to a report from The National Interest. Now, in the process of opening up the equipment, the individuals broke down the DUV machinery.

This is actually interesting and hilarious at the same time. While the report doesn't pinpoint the specific source of this development, the occasion doesn't seem too far-fetched, considering China's 'hunger' for a breakthrough in the chip industry. Now, once the machines broke down, Chinese engineers actually called out ASML to fix the machines, but the Dutch firm discovered the intentions of the engineers involved. The report has yet to be verified by ASML for now.

Although these poor bastards are probably destined to be organ donors, I give them credit for trying. Farting in the same room with them installed would probably put those machines out of commission for three months. Semiconductor manufacturing id that delicate.

Actually China is having problems smaller than 14nm.
They can build them but they don’t operate at full speed and yield is very poor.
Without EUV lithography, 7nm and smaller is virtually impossible.
Both Intel and Global Foundry discovered this.
Intel pushed very late into EUV and GF abandoned anything smaller than 14nm.

ASML is the only way to make EUV work and it took them 25 years to make it work.

I read recently that terms like “3 nm”, “7 nm” etc. are more *marketing* terms than actual dimensions. State-of-the-art semiconductors for CPUs/GPUs/NPUs are so complicated in structure (FinFET, RibbonFET, GAAFET, MBCFET etc.) that there are many dimensions involved, almost none of which are actually that small.

Excerpt (from “https://en.wikipedia.org/wiki/3_nm_process“):

“The term “3 nanometer” has no direct relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 3 nm node is expected to have a contacted gate pitch of 48 nanometers, and a tightest metal pitch of 24 nanometers.[12]

“However, in real world commercial practice, 3 nm is used primarily as a marketing term by individual microchip manufacturers (foundries) to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption.[13][14] There is no industry-wide agreement among different manufacturers about what numbers would define a 3 nm node.[1]

I used to know a senior executive at ASML - they moved all of their operations to Singapore (at a higher cost) a long time ago because they knew China would steal anything they could. I imagine national boundaries are less of a barrier to that effort now than they used to be.

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