Posted on 02/08/2010 6:15:38 AM PST by Ernest_at_the_Beach
The semi-annual dance of chip technology previews gets its 2010 start at the International Solid State Circuits Conference in San Francisco two weeks from now, and Intel, Advanced Micro Devices, IBM, Sun Microsystems (soon to be a division of Oracle), and Hitachi are going to be talking up their future chip tech.
Intel's chip geeks will be showing off the company's "Westmere" family of 32 nanometer processors, which already made their debut earlier this month inside desktop and laptop machines and which are expected to come out for servers within the next couple of months. The details on the session being hosted by Intel at ISSCC are pretty skinny, as you can see from the advanced program. But the word on the street is that Intel will be showing off improvements to the QuickPath Interconnect and low-voltage DDR3 buffers added with the Westmere tweaks.
Intel is showing off another chip which is sure to raise some eyebrows. The company's chip design teams in the United States, India, and Germany have cooked up a 48-core, 32-bit x86 chip implemented in 45 nanometers. This chip, which implements a 2D mesh network in a six-by-four core array, uses message passing across a 384 KB on-die shared memory and also sports fine-grained power management through a feature called dynamic variable frequency scaling (DVFS), which allows individual cores to run at eight different voltages and 28 different frequencies. In the performance range Intel has set up for the chip, power dissipation for this baby x86 supercomputer cluster on a chip (well, that is essentially what it is) ranges from 25 to 125 watts.
Intel will also be discussing a streaming circuit switch, suitable for linking computing elements on a chip in an 8-by-8 2D mesh together, that is also implemented in 45 nanometers and that provides 4.1 Tb/sec bisections and 560 Gb/sec of aggregate bandwidth. This mesh network was cooked up in Intel's Hillsboro, Oregon, facility. This mesh network burns 4.73 watts at 1.1 volts and the network links can apparently be pushed up to 6.43 Tb/sec. No word on how this mesh network will be used by Intel.
Rival AMD will be showing off a new core design implemented in 32 nanometers using silicon-on insulator processes. This core, says the ISSCC abstract, will have more than 35 million transistors (excluding its L2 cache memories) and will crank its clocks up beyond 3 GHz. The AMD chip will have a power dissipation range of between 2.5 and 25 watts, including a zero-power gated state, and will be aimed at desktop and mobile computers. This core is very likely the one that will be launched in the Fusion family of processors, which will pack CPUs and GPUs on the same piece of silicon. (See El Reg's review of the AMD desktop and mobile roadmaps here.)
IBM is announcing its Power 7 Server Products and Intel is suppose to be announcing it’s Tukwila Server processor also today.
IBM shows off Power7 HPC monster
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This server node is the heart of the 1 petaflop "Blue Waters" supercomputer being installed at the University of Illinois. (That's sustained, not peak, performance.)
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AMD outlined its product roadmaps through 2011 for servers, desktops, and notebooks on Wednesday during the company's financial analysts' day at its Sunnyvale, California, headquarters.
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Bobcat will be aimed at the other end of the power and performance spectrum: ultra-thin notebooks. Designed to require less than a watt of power, Bobcat will, AMD claims, provide 90 per cent of "today's mainstream performance" in less than half of the current silicon real estate - though exactly how the company defines "mainstream performance" remained unstated.
Both the Bulldozer and Bobcat cores are being designed to be highly scalable and able to be combined with GPU circuitry and other IP assets into application-specific APUs.
Power7 power lunch and launch next Monday Feb 8 2010
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The word on the street, which has not (and will not) be confirmed by IBM is that the company is going to start its rollout of Power7-based machines at the bottom of the product line, which makes sense if yields are relatively low on the eight-core chips.
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