Posted on 02/12/2006 1:19:36 PM PST by Ernest_at_the_Beach
IBM has unveiled its first servers powered by the high-performance Cell processor, which at first was earmarked for next-generation gaming consoles. The new servers, which will be available in June, initially will target customers doing graphics-intensive data-crunching.
Big Blue's new blade systems are based on the Cell Broadband Engine (Cell BE) with a configuration that is significantly different from typical desktop or server chips. Cell can handle significantly more floating point operations than other processors, said Darryl Solie, distinguished engineer in IBM's Systems and Technology Group.
Cell technology, which was developed jointly by IBM, Sony, and Toshiba, is optimized for media applications such as games, movies, and other digital content. It will power the forthcoming Sony PlayStation 3 console.
Not Just Playing Games
Beyond entertainment computing, the Cell chip will offer native support for multiple systems, including Linux and consumer-electronics applications. The three partners project that a Cell-based workstation soon will reach a processing-performance level of 16 teraflops -- or 16 trillion calculations per second. In contrast, a general-purpose PC typically has a rating of only a few billion operations per second.
The Cell is not a general-purpose CPU because it is optimized for certain applications. But if the teraflop rating were the only measure of system performance, the Cell chip would place the PlayStation 3 in the top 100 fastest supercomputers on the planet. IBM's BlueGene/L, for example, currently ranks at the top of the supercomputer chart on Top500.org with a peak performance of 183 teraflops.
In addition to powering the PlayStation 3 console and media-server products planned by Sony and Toshiba for the home, the Cell processor also will be used for computers created for medical, aerospace, and defense applications. Toshiba plans to launch its first Cell-based HDTV in 2006.
Business Applications
The Cell BE-based system previewed this week by IBM is designed to handle supercomputing-type chores, including 3D rendering, data compression, and encryption.
"It is particularly useful in applications like CT and MRI medical imaging, improving the processing of these types of high-resolution images," Solie said. The government also has shown a strong interest in Cell technology, he added, for use in radar-signal processing.
Solie said that Cell chips won't displace the mainframes found in most enterprise environments, but he said they will be useful for Web services and communications.
IBM recently announced a partnership with Mercury Computer Systems, which last month shipped its first Cell Technology Evaluation System, a turnkey system that features the Cell BE processor and an Intel Architecture development environment.
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A brief view of CBEA's tripartite organization of storage and its programming implications
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Level: Introductory
Dr. H. Peter Hofstee (hofstee@us.ibm.com), Architect, IBM
24 Aug 2005
The Cell Broadband Engine Architecture (CBEA, or, informally, "Cell") defines a new processor structure based upon the 64-bit Power Architecture™ technology, but with unique features directed toward distributed processing and media-rich applications. The Cell architecture defines a single-chip multiprocessor consisting of one or more Power Processor Elements (PPEs) and multiple high-performance SIMD Synergistic Processor Elements (SPEs). While each SPE is an independent processor running its own application programs, a shared, coherent memory and a rich set of DMA commands provide for seamless and efficient communications between all Cell processing elements. This article provides a concise view inside the Cell's architecture.
The first generation Cell Broadband Engine is the first incarnation of the new family of microprocessors conforming to the CBEA. The CBEA is a new architecture that extends the 64-bit Power Architecture technology. The CBEA and the Cell Broadband Engine are the result of a collaboration between Sony, Toshiba, and IBM known as STI, formally started in early 2001.
Although the Cell Broadband Engine is initially intended for application in game consoles and media-rich consumer-electronics devices, the architecture and the Cell Broadband Engine implementation have been designed to overcome some of the fundamental limitations to processor performance. A much broader use of the architecture is envisioned.
The Cell Broadband Engine is a single-chip multiprocessor with nine processors operating on a shared, coherent memory. In this respect, it extends current trends in PC and server processors.
The most distinguishing feature of the Cell Broadband Engine is that although all processors share main storage (the effective-address space that includes main memory), their function is specialized into two types -- the Power Processor Element (PPE) and the Synergistic Processor Element (SPE). The Cell Broadband Engine has one PPE and eight SPEs.
The SPEs are independent processors, each running its own individual application programs. Each SPE has full access to coherent shared memory, including the memory-mapped I/O space. The designation synergistic for this processor was chosen carefully -- there is a mutual dependence between the PPE and the SPEs. The combination of the two working in harmony produces a greater effect than each working alone. The SPEs depend on the PPE to run the operating system and, in many cases, the top-level control thread of an application. The PPE depends on the SPEs to provide the bulk of the application performance.
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The SPEs are designed to be programmed in high-level languages and support a rich instruction set that includes extensive single-instruction, multiple-data functionality (SIMD). However, just like conventional processors with SIMD extensions, use of SIMD data types is preferred but is not mandatory. For programming convenience, the PPE also supports the Power Architecture Vector/SIMD Multimedia Extension.
To an application programmer, the Cell Broadband Engine looks like a nine-way coherent multiprocessor. The PPE is more adept at control-intensive tasks and quicker at task switching. The SPEs are more adept at compute-intensive tasks and slower at task switching. However, either processor is capable of both types of functions. This specialization has allowed increased efficiency in the implementation of both the PPE and the SPE (especially the SPE), and is a significant factor in the substantial performance improvement in applications which take advantage of the CBEA.
The more significant difference between the SPE and PPE is in how they access memory. The PPE accesses main storage (the effective-address space that includes main memory) with load and store instructions that go between a private register file and main storage (which may be cached), whereas the SPEs access main storage with DMA commands that go between main storage and a private local memory used to store both instructions and data. SPE instruction- fetches and load and store instructions access this private local store rather than shared main storage.
This three-level organization of storage (register file, local store, main storage) -- with asynchronous DMA transfers between local store and main storage -- is a radical break with conventional architecture and programming models because it explicitly parallelizes computation and the transfers of data and instructions.
The reason for this radical change is that memory latency, measured in processor cycles, has gone up several hundredfold in the last 20 years. The result is that application performance is often limited by memory latency rather than peak compute capability or peak bandwidth. When a sequential program on a conventional architecture performs a load instruction that misses in the caches, program execution now comes to a halt for several hundred cycles. Compared with this penalty, the few cycles it takes to set up a DMA transfer for an SPE is quite small. Even with deep and costly speculation, conventional processors manage to get at best a handful of independent memory accesses in flight. The result can be compared to a bucket brigade in which a hundred people are required to cover the distance to the water needed to put the fire out, but only a few buckets are available.
In contrast, the explicit DMA model allows each SPE to have many concurrent memory accesses in flight without the need for speculation.
The most productive SPE memory-access model appears to be the one in which a list (such as a scatter-gather list) of DMA transfers is constructed in an SPE's local store so that the SPE's DMA controller can process the list asynchronously while the SPE operates on previously transferred data. In several cases, this new approach to accessing memory has led to application performance exceeding that of conventional processors by almost two orders of magnitude, significantly more than anyone would expect from the peak performance ratio (about 10x) between the Cell Broadband Engine and conventional PC processors.
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This article provided a brief introduction to the Cell Broadband Processor Architecture and gave a rationale for the major design decisions in the architecture.
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Dr. H. Peter Hofstee is the chief architect of the Cell Synergistic Processor, and Cell chief scientist. He received his PhD in computer science from the California Institute of Technology (Caltech) in 1995, and joined the Caltech faculty in 1995 and 1996 to teach computer science and VLSI. In 1996 he joined the IBM Austin research laboratory where he helped create the first GHz CMOS processor. Between 1997 and 2000 he worked on a number of other high-frequency server processor designs. In 2000 he helped create the concept for Cell and became one of the founding members of the STI (Sony -Toshiba - IBM) design center in the spring of 2001. His current interest focuses on application of the Cell processor beyond the gaming space and on future Cell designs. |
And it is a single chip....just astounding!!!
Gonna run Linux too...
Wonder if a "Smart" Fortran compiker is to be designed for this?
It is amazing that IBM can be at the forefront of computer science and tech for so long and still not dominate the entire industry.
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Linux on CBE-based systems
The Linux on CBE-based Systems Web site at the Barcelona Supercomputing Center (BSC) aims to provide information about how to enable Linux on CBE platforms. In addition to hosting the above Linux kernel patch for the CBE and SPE Management Library, it also hosts the GNU toolchain for a native or PowerPC® development environment.
It is a super competitive industry!
BSC received two Cell Broadband Engine based blades last October 2005. Since we now have hardware available, we have been able to test packages and the Fedora Core installation instructions on a real Cell Broadband Engine Architecture (CBEA).
These are some photos of the Cell-blades:
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Found some pictures...
"It will power the forthcoming Sony PlayStation 3 console."
Due out next month.
Specs:
http://www.ps3land.com/ps3specs.php
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Well, I was thinking about buying one....
Not a chance. IMHO, we will be lucky if we see it before Dec or possibly Q1 2007.
Also I believe the "Revolution" will be a kick-a$$ system. :-)
I already have the XBox-360, and will get both of these as well when available.
What's under the covers of the Revolution?
Actually not sure. They are keeping the Rev pretty close to the chest so to speak. It will be really diff than either the 360 or the PS3. The controller looks out of this world. :-)
It will prob be about 2-3 times more powerful than a GameCube.
A PS3, you mean? It won't be a bad move. Just don't expect the console any time soon, or a great library of games for the first few months after its launch.
I think the PS2 is the best value in gaming right now, but the PS3 is backwards-compatible, so you can always pick up the PS2 games now and play them later on your PS3...
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