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To: N3WBI3; KwasiOwusu
Last time Im going to point this out to you Pentium=CISK, G4=RISK. Those are not only two different processor architectures those are two completely different design methodology.

RISC. Anyway, both of you might want to check the Ars Technica article on the difference between a G4 and a Pentium 4. But remember that the article is outdated as the G4 has had a couple generations of technical improvements since then.

KwasiOwusu, I expect you to have read this if you comment any further based on clock speed. But to sum it up, the P4 executes a small number of instructions per cycle, but cycles very quickly. The G4 processes a larger number of instructions per cycle, but cycles more slowly. In other words, a four-line highway of 40mph cars doesn't carry more traffic than a two-lane highway of 80mph cars (aside from any real-world traffic engineering considerations).

Ramping the clock speed at the expense of efficiency was simply a marketing tactic of Intel's at a time when GHz was popularly seen as an indicator of how fast a processor is. It was exceptionally embarrassing when the first Pentium 4 at 1.5GHz was actually slower than the latest Pentium III at a much lower clock.

Given that Intel has followed AMD's lead in not naming the processor by its clock speed anymore, it's apparent that Intel has abandoned clock speed and started to look at efficiency -- just like the G4 and AMD chips had all along. Of course that could have something to do with the fact that they hit a wall on the clock speed ramp.

247 posted on 01/12/2005 10:00:16 AM PST by antiRepublicrat
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To: antiRepublicrat

ug cant believe I made that mistake.... thanks for the heads up..


248 posted on 01/12/2005 10:05:00 AM PST by N3WBI3
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To: antiRepublicrat

Realistically, it seems to me that RISC vs. CISC is kind of a red herring these days, as the answer of which one is "better" is more or less "both", given the evolution of processors over the last decade. Comparing the current (fairly large) PPC instruction set to, say, the original MIPS instruction set doesn't make PPC look very RISC-ish when they're put side by side. Contrariwise, despite the x86 instruction set, the P4 decodes x86 instructions into what are quite RISC-like micro-ops. Honestly, it looks very much like the "RISC revolution" resulted in chips that are hybrids, capturing the best aspects of both philosophies, more than anything else.


264 posted on 01/12/2005 10:57:02 AM PST by general_re (How come so many of the VKs have been here six months or less?)
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