I was intrigued with RISC back then. Made sense; let the software do the heavy lifting. Then again, at the time software sucked and hardware was slow. Better to let the silicone do the heavy lifting with the clock speed available.
CISC can’t keep up. And RISC is more flexible.
re: “CISC can’t keep up. And RISC is more flexible.”
This isn’t your grandpa’s CPU world anymore; instruction ‘pre-fetch’ and multi-branch decode has changed ALL that ...