Posted on 10/15/2002 7:59:59 PM PDT by HAL9000
Microprocessor Forum IBM's Peter Sandon disclosed technical details for IBM's PowerPC 970 processor in San Jose this morning and confirmed that the processor supports the AltiVec instruction set. In addition to providing a competitive workstation and edge server chip for IBM - which deploys POWER3 in these space and power sensitive designs, the processor is tailor made for high end Apple machines. It's expected to sample in the first half of next year, and appear in production volumes in the second half.970 is a single 64bit core - as opposed to today's POWER4 - with IBM predicting 937 SPECint2000 and 1051 SPECfp2000 at 1.8Ghz, and 5220 MIPS. Initial quantities will debut at 1.4 to 1.8Ghz, with 512kb of Level two cache. In his presentation, he described these as "conservative" estimates.
There are two SIMD execution units (IBM doesn't use the word 'Altivec' in the presentation); 9 fetch/decode stages and up to 8 issues per cycle.
32bit code runs natively on the 970, says Sandon. "There is no emulation," he explained. 32bit operating systems need to be modified but the list of modification is not large.
Power consumption is specified as 42W at 1.8Ghz (1.3v) and 19W at 1.2Ghz (1.1v). IBM says the processor has the same core voltage (1.3v) as the Motorola 7455 that forms the mainstay of Apple's desktop line.
Apple confounded expectations by opting to use higher frequency 7555 processors in its professional G4 tower machines this summer, instead of Motorola's 7470. With a year to go before Apple can use POWER4-lite, why even bother supporting its joint IBM-Motorola BookE-compliant sibling, G5?
Tom Halfhill of MDR, which is hosting the conference, said the 970 would still be slower than x86, but that performance should be better than clock speeds imply.
"Now that Apple has a real workstation-class and server-class OS, it needs a real workstation-class and server-class processor," he said.
The 970 smokes today's desktop competition in terms of raw number crunching. By way of contrast, AMD told us today that when Opteron debuts in the first half of next year it will ratchet up a SPECint of 1202 and a SPECfp of 1170. These, AMD's John Crank told us, were based on real silicon. Nothing stands still in this business. ®
IBM Discloses 64-bit PowerPC Details
The Heart of the Next Mac?
By Mark HachmanSAN JOSE-IBM described its latest 64-bit PowerPC Tuesday morning, a chip that analysts are already speculating will form the engine inside the next Apple Macintosh computer.
On paper, the new PowerPC 970 chip looks quite impressive. IBM has taken its high end Power4 architecture—which, for servers, combines several processor cores on one chip—and reduced it down to a point where it can fit inside a desktop computer. As is the case when a new PowerPC chip is introduced, analysts began speculating as to who may buy it.
"They can't say Apple, but we can, speculatively, of course," said Tom Halfhill, an analyst with MDR/In-Stat, the hosts of the show here.
The PowerPC 970 triples the length of the PowerPC pipeline, which translates into a higher clock speed: 1.4 to 1.8 GHz at the core's introduction, according to Peter Sandon, senior processor architect within the PowerPC organization at IBM Microelectronics.
Perhaps more importantly, the front-side bus can transfer up to 7.2 Gbytes per second, roughly four times the bandwidth of the current Pentium 4 front-side bus, according to MDR's Halfhill. Finally, the core uses a single-instruction multiple-data unit (SIMD), which actually uses the same 162 instructions as Motorola's Altivec engine. Due to copyright restrictions, however, IBM can not use the Altivec name.
"If I were designing a processor for high end graphics desktops or servers this is what it would look like," Halfhill commented.
The PowerPC 970 will sample in the second quarter of 2003 and should be shipping in volume by the end of the year, probably meaning that Apple or some other customer would be able to release systems early in 2004. The chip will sample roughly a quarter or two later than AMD's own Hammer processor, due to ship in the first quarter of 2003.
"Our goal in designing the PowerPC 970 was to enable (symmetric multiprocessing) while still supporting 32-bit code with a high level of performance," said Peter Sandon, senior processor architect within the PowerPC organization at IBM Microelectronics.
Like the Hammer, the PowerPC 970 contains a 32-bit compatibility mode. All addresses and fixed-point operands are treated as 32-bit entries, Sandon said. In addition, the company has successfully booted and run 32-bit and 64-bit versions of Linux in the lab.
"Changes are necessary to port 32-bit OS to a 64-bit processor but the list of changes is small," Sandon said.
The core, as defined, contains 64 Kbytes of instruction cache, 32 Kbytes of data cache, and 512 Kbytes of 8-way set associative level 2 cache. Unlike the Power4, the core does not apparently contain an onboard cache controller to enable the use of off-chip L3 cache.
The front-side bus electrically runs at 450-MHz, double-clocked to an effective rate of 900-MHz, generating a peak bandwidth of 7.2 Gbytes or 6.4 Gbytes/s of useable bandwidth after transaction overhead is taken into account, Sandon said. Five instructions can be issued and acted upon at any one time, while a total of 200 instructions can be "in flight" at any time, taking into account instructions that are stored in queues.
Performance-wise, IBM believes the chip can record a benchmark of 932 on SPECint 2000 and a score of 1051 on SPECfp2000, both at 1.8-GHz. Peak SIMD GFLOPs should be about 14.4, Sandon said. Using Dhrystone MIPS, the chip should output a score of 5,220. or 2.9 DMIPS/MHz/. IBM expects the chip should test 18 million RC5 keys per second.
IBM will use a 0.13-micron SOI process with 8 levels of copper to manufacture the chip, which should require a 576 pin package; Sandon did not disclose the die size. IBM expects the chip will output between 19 watts and 42 watts of power, depending on the whether a 1.2-GHz (1.1 volts operating voltage) or 1.8-GHz (1.3 volt) clock speed is used.
The PowerPC 970 is actually not the first 64-bit PowerPC architecture; Motorola announced the PowerPC 620 in 1998 as one of the first PowerPC implementations. However, the core required over four years to commercialize, and was an "instant flop", Halfhill said.
"The PowerPC 64-bit history is not very stellar but they're going to try again," Halfhill said.
No performance numbers making their way into the press yet?
Any hints as to how they perform and how stable and how hot they are?
AMD Tips "Clawhammer" Benchmarks
A single Opteron core running at an actual clock speed of 2.0-GHz with registered PC2700 memory yielded a SPECint2000 score of 1202, and a SPECfp2000 score of 1170, Weber said.
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