Seriously, I've heard about many techtologies over the years: Germanium, gallium-arsenide. This particular one seems to imply a completely different manufacturing process.
One of the limitations of traditional N- and P- doped silicon is the atomic size difference between boron (+) and phosphorus (-). Even though CMOS stands for complimentary metal oxide semiconductor, the P-channel devices run at only about half the speed as their N- counterparts. This is why, in the early days before CMOS dominance, it was NMOS devices that were typically seen in early IC memory and microprocessor applications. Very few IC's employed PMOS, and all without exception that I can think of were linear, analog applications. I never quite understood why - cleaner signals maybe?
The key will be attaining a high yield rate with an inexpensive manufacturing process. The article hints at one of the upcoming challenges to this:
Current fabrication techniques produce a mix of nanotubes with different sizes and electronic properties, not all of which will work well in integrated circuits.
Actually, the first calculators and similar devices were PMOS. I don't know the details, but I think the process was easier. Also, PMOS could run at higher voltages, allowing them to drive vacuum fluorescent and neon-discharge based displays directly, whereas NMOS or CMOS could not (easily).