Posted on 01/04/2023 4:44:02 PM PST by FarCenter
In a recent guest editorial here on EE Times, legendary professor David Patterson wrote about busting the five myths around the RISC-V instruction set architecture (ISA). At the recent RISC-V Summit organized by RISC-V International, the consortium that manages and promotes the RISC-V Instruction Set Architecture (ISA), its president, Calista Redmond, had a far more blunt message: RISC-V is inevitable.
In fact, she said, RISC-V will eventually have the best CPUs, the best software running on them and the best ecosystem of any microprocessor core family. These are mighty strong words for a nascent ISA that is only about 10 years old and that competes with the far more established Arm and x86 ISAs. It almost sounded like the Borg from Star Trek when they say, “Resistance is futile.”
Redmond’s reason for saying that RISC-V is inevitable is that its growth and success are built upon shared investments of many companies, universities and contributors. RISC-V International has more than 3180 members. Billions of dollars have been invested in the architecture, including national programs from countries and regions such as India and the E.U. This enables the development of the “best” processor in multiple price and performance categories with the contributions of so many ideas and collective knowledge. Because RISC-V is scalable, customizable and modular, it can easily be optimized for different workloads and applications.
The software ecosystem is growing, and efforts are underway to make software development more efficient with profiles and standards like a single hypervisor standard.
(Excerpt) Read more at eetimes.com ...
Calista Redmond is CEO of The RISC-V Foundation and a longtime tech executive. Redmond joined the RISC-V Foundation in March 2019.[1] Prior to her appointment, she spent 12 years at IBM and was vice president of the IBM Z ecosystem from 2016 to 2019.[1] As part of her work at IBM, Redmond was a director at OpenPOWER and was also involved with OpenDaylight and Open Mainframe Project.[2] Redmond received her MBA from the University of Michigan’s Ross School of Business in 2006 and her BS from Northwestern University in 1996.
https://en.wikipedia.org/wiki/Calista_Redmond
IBM is a founding member of the RISC-V Foundation.
Apple started seeking RISC-V engineers about 16 months ago.
Idiots. All your CPU ARE belong to us. That’s what made it funny in the first place.
RISC stands for “Reduced Instruction Set Computer”. Here the V stands for the Roman number 5. Hence RISC-V is the 5th Generation of a family of computer cores. It is pronounced “RisK Five”. Unlike most other ISA designs, the RISC-V ISA is provided at no cost with an open source license. RISC-V does not require a license because it is Open Source and Open Architecture which means that the design can be modified and special instructions can be created to improve performance or make life difficult for hackers. For more information view the introduction guide to RISC-V e-book linked here.
Shes got the wild crazy eyes of the gal who just got sentenced for scamming investors.
Back to the Future!
In 1984, a small team of Sun engineers set out to develop a 32-bit RISC processor called SPARC (for Scalable Processor Architecture). The idea was to use the chips in Sun’s new line of workstations. One day, Scott McNealy, then Sun’s CEO, showed up at the SPARC development lab. “He said that SPARC would take Sun from a $500-million-a-year company to a billion-dollar-a-year company,” recalls Patterson, a consultant to the SPARC project.
...
The first version of the minimalist SPARC consisted of a “20,000-gate-array processor without even integer multiply/divide instructions,” says Robert Garner, the lead SPARC architect and now an IBM researcher. Yet, at 10 million instructions per second, it ran about three times as fast as the complex-instruction-set computer (CISC) processors of the day.
https://spectrum.ieee.org/chip-hall-of-fame-sun-microsystems-sparc-processor
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