[Ernest_at_the_Beach]

ping

[DesScorp]

It’s bad branding to label the new ARM chips “Opteron” when that’s already the established name of their X86-64 server chips.

[JRandomFreeper]

I like that... Legacy networking = 10GbE.

/johnny

[Dalberg-Acton]

If not for AMD, Intel CPUs would be at least twice the price.

[SunkenCiv]

There's only a single die mask so we're talking about harvested die to make up the quad-core configuration... Each core will run at a frequency somewhere north of 2GHz. The SoC is built on a 28nm process at Global Foundries. Each pair of cores shares a 1MB L2 cache, for a total of up to 4MB of L2 cache for the chip. All cores share a unified L3 cache of up to 8MB in size... a new memory controller... capable of supporting both DDR3 or DDR4. The memory interface is 128-bits wide and supports up to 4 SODIMMs, UDIMMs or RDIMMs. AMD will be shipping a reference platform capable of supporting up to 128GB of Registered DDR3 DIMMs off of a single SoC. Also on-die is an 8-lane PCIe 3.0 controller (1 x8 or 2 x4 slot configurations supported) and an 8-port 6Gbps SATA controller. AMD assured me that the on-chip fabric is capable of sustaining full bandwidth to all 8 SATA ports.

Will, will be, assures, capable of, harvested die -- IOW, it ain't ready yet. Too bad, an ARM server is a good approach.