I'm sorry, I thought it was you who I was previously discussing the Cell with.
From what I heard in a usual batch some chips will be useless (errors in the PPC CPU, multiple SPE cores or elsewhere), some will have an error on just one SPE core (they comprise about half of the chip area) and some will be pristine. After testing they use all the chips in the middle case and blow one core on the last case to keep everything consistent. The alternative would be to set the PS3 standard to all eight cores and they'd have to throw away all those chips with just one defective core.
I'm not familiar with the Cell--does it really only have 7 cores?
Eight cores, seven active in the PS3 due to yield considerations as discussed above, six available to developers (the last reserved for the PS3's OS). I was just thinking to use the pristine ones for these applications and the seven-core ones for the PS3 market.
That center bus between the elements is over 200 GB/sec, the memory interface on the left is over 25 GB/sec, the I/O on the right is over 60 GB/sec. Pretty spiffy, huh? I like how the SPEs are lined up mirror-image.
I know HPL would probably run more efficiently on 8-core chips.
You can go one of two ways: Parallelize the task and have all six SPEs working on equal chunks of the larger problem, or serialize the task and have each SPE work on a part of the larger problem then pass the problem down for further processing while it receives its chunk of the next problem. Each SPE has IIRC 256K of fast local SRAM, so you can probably store a smaller program and fit more of a working dataset in there when serializing without having to go out to main memory as much.