[tortoise]

Due to Stanford using an Intel compiler, these problems will run faster (2x reportedly) on Intel hardware with SSE2. Some AMD cpus have SSE2, but the Intel compiler doesn't take advantage of it.

Interesting, since GCC 4.x generally produces code that is competitive with the Intel compiler speed-wise, without the Intel bias. The Pathscale AMD64 compilers (popular with high-performance apps) can suck an amazing amount of floating point performance out of AMD hardware, but you have to pay for the privilege. Most of these problems appear to be better suited to AMD than Intel, based on a loose survey of typical parameterization. Same ISA, significantly different design choices.

[HangThemHigh]

You obviously no a lot more about compilers than I do, but there has been a good bit of discussion about this on the Folding forums which might interest you. Unfortunately I have not kept links to the discussions.

Stanford has a rational for using the Intel compiler. I seem to recall they claimed it produces faster code than the AMD compiler, which was the only other candidate even close in terms of speed.

They say that are working to resolve the problem.

[HangThemHigh]

More AMD & SSE2 Info (with links)

This states: "...for the time being the AMD CPUs will not get any QMD WUs"