IBM demonstrated a blade server board based on the Cell architecture at the E3 show this week, and reportedly plans to sell the boards in rack-based server systems.

The board carried two Cell processors running at up to 2.8Ghz, as well as 1GB of DRAM split across two chips, according to Nikkei’s TechOn service (http://techon.nikkeibp.co.jp/english/NEWS_EN/20050525/105050/). The demo box ran on Linux.

The chips have been clocked at 3GHz in the lab, according to an IBM engineer quoted by TechOn, meaning theoretical performance of 400Gflops for a two chip board.

Unsurprisingly, perhaps, the demo board featured chunky heatsinks and fans. However, IBM expects to be able to use thinner heat sinks which will allow it to squeeze seven of the boards into a rackmount chassis.

The massively parallel architecture has been jointly developed by IBM, Sony and Toshiba, and so far they seem to be pitching it at every market that comes to mind, from consoles, to PDAs, mainstream computers, and digital home appliances.

That Cell will be underpinning Playstation 3 is no secret. That IBM chose E3 to demo the dual-processor blade board may point to the company’s designs on compute intensive entertainment market. Hollywood is gobbling up computer capacity, while the onset of HDTV, for example, is expected to put massive demands on broadcasters’ tech resources. Or perhaps the engineers had simply lashed together the board and just wanted to show off their work.

IBM already has one of the more diverse blade server lines around with Xeon-, Opteron- and its homemade Power-based systems. ®

The Cell chip - what it is, and why you should care

By Andrew Orlowski in San Francisco (andrew.orlowski at theregister.co.uk)

Published Tuesday 1st February 2005 22:07 GMT

Analysis No chip in years has caused as much excitement as the Cell processor developed by IBM, Sony and Toshiba. It promises to be the most important microprocessor of the decade, with potentially enormous repercussions for how the industry computes, and how the rest of us use digital media. It will power the PlayStation 3 and technical and commercial computing.

Technical details of Cell will be disclosed at the International Solid State Circuits Conference in San Francisco next week, and in anticipation we'll look first at how the Cell works and then tomorrow at what it means to the industry and consumers.

Excitement about Cell has already led to some wild and poorly informed speculation, as Ars Technica's Jon Stokes rued (http://arstechnica.com/news.ars/post/20050124-4551.html) last week. But earlier in the month, Microprocessor Report's Tom Halfhill published an investigation into a detailed patent filed in 2001, and published by the USPTO in October, and he was kind enough to discuss it with us. We'll refer to it as the '734 patent.

Inside Cell

The ambitious scale of the project is one of the most remarkable aspects of Cell.

"It isn't just a single microprocessor or even a family of processors," writes Tom. "It's a top-to-bottom architecture for a broad range of computing systems, from servers and workstations at the high-end to game consoles, PDAs, digital TVs, and other consumer electronics at the low end".

How does it look?

The 'cell' which gives the chip its name doesn't refer to the hardware, but to a virtual clump of software which roams the system looking for computing resources. The patent refers to a "cell object" - program and data - and it can even roam across LANs or WANs, to find another Cell-based device.

A Cell chip consists of one or more independent execution units, and a program can commandeer as many of these as resources allow to create a temporary execution pipeline, each with its own register file and banks of RAM. These pipelines are dynamically configurable and can lock out other processes from grabbing their hardware resources. "The Cell architecture introduces a whole new meaning to the term 'self-modifying code'," notes Tom drily.

The '734 patent calls the basic hardware unit a PE, or 'processor element'. Rather confusingly, a PE consists of a 'processor unit' or PU, and an array of attached, er, processing units or APUs. The patent, Tom notes, says that the "preferred" PE configuration is eight APUs. The "preferred embodiment" of an APU is 128kb of SRAM, 128 x 128-bit registers, four integer units and four floating point units. Some of these may be specialized for tasks such as shading.

Inside each software cell are 'apulets'. These aren't necessarily self-contained programs, stress MPR, but seem more like serialized objects. Amongst the many mysteries yet to be revealed about software cells is how the chip schedules such tasks, not just amongst onboard PEs but also amongst other Cells.

"Imagine an apulet running on your PDA that depends on a result coming from another apulet running on a computer in Norway," writes Tom. The Cell processor must make its best guess, based on network latencies, how to distribute the workload. The designers have set themselves an awesome challenge.

Halfhill also notes that the Cell's architecture is more flexible than Java's sandboxes, because a software cell can encapsulate several processes, or part of a single process. There's no evidence, he points out, that Cell implements JVMs in hardware: it's much more subtle than that. For security purposes, Cell's hardware restrictions may prove to be the most controversial aspect of the chip.

Some interesting design decisions have been made in creating the memory architecture -

"It’s hard to avoid the conclusion that Cell processors will have an extraordinarily secure but cumbersome memory model. For each main-memory access, the processor would have to consult four lookup tables... Three of those tables are in DRAM, which implies slow off-chip memory references; the other table is in the DMA controller’s SRAM. In some cases, the delays caused by the table lookups might eat more clock cycles than reading or writing the actual data. The patent hints that some keys might unlock multiple memory locations or sandboxes, perhaps granting blanket permission for a rapid series of accesses, within certain bounds."

Global security

The Cell architecture isn't just a blueprint for a new kind of chip, but for a massively distributed global computing network. Each Cell is given a GUID, a global identifier. Your PlayStation may be hosting processes that began life on a Cell on another side of the world. Remember that the architecture enables a strict, lock-down machine to be built, with access to memory tightly controlled. Since DRM is predicated on controlling uniquely-identified media to run, or not run, on a specifically-authorized piece of hardware, this allows system designers much more scope in building systems which can both restrict and track the content they play.

There may be more benign uses: Cell clearly makes a very sophisticated building block for distributed grid computing too. "A hypothetical Cell processor with eight of these APUs could achieve 32 BOPS and 32 gigaFLOPS at only 250MHz," writes Tom. Or a teraflop at 1Ghz. This is an order of magnitude higher than today's workstations in what could be a low cost, low power machine. If Cell fulfills its promise, Intel is facing its greatest challenge since the turn of the 1990s, when RISC processors seemed to be extending an unbeatable performance lead, and when Microsoft was porting Windows NT to every RISC platform it could: MIPS, Alpha and PowerPC. But the remarkable P6 core (which first appeared in the Pentium Pro) saw the performance gap narrow, and the alliances arrayed against Intel stumbled and fragmented.

This time, Cell is aimed at a different market, one that Wintel has failed to conquer - the living room. ®

Sony Cell CPU to deliver two teraflops in 64-core config

By Tony Smith (tony.smith at theregister.co.uk)

Published Wednesday 5th November 2003 12:11 GMT

'Cell', the massively parallel processing chip currently being designed by Sony and IBM, will scale from single-chip systems through to entire server rooms packed with thousands of them, Sony's executive deputy president Ken Kutaragi told attendees of the company's Transformation 60 conference yesterday.

That's always been the goal, of course, since Cell was first announced (http://www.theregister.co.uk/content/3/17511.html) back in March 2001. But yesterday Kutaragi put some numbers onto the chart.

A four-core chip home server system will be able to deliver one billion floating-point operations per second, apparently. Move up to a 32-core chip - in, say, a blade server module - and you'd get 32 gigaflops of processing power, while a 64-core slab of silicon inside a rack-mount unit doing graphics work would churn out two teraflops, according to Kutaragi's presentation foils.

Ultimately, Kutaragi suggested, we'll see 16 teraflop supercomputer 'cabinets' and one petaflop (a million billion flops, in other words) server rooms - the latter delivering enough raw power for true AI systems, he said.

Kutaragi likened a single Cell chip to IBM's 32-node RS/6000-based chess supercomputer Deep Blue. The exponential scaling rate suggests Cell really doesn't come into its own until you use lots of them together.

That's certainly the design philosophy: "With built-in broadband connectivity, microprocessors that currently exist as individual islands will be more closely linked, making a network of systems act more as one, unified 'supersystem'. Just as biological cells in the body unite to form complete physical systems, Cell-based electronic products of all types will form the building blocks of larger systems," was how Kutaragi described the Cell concept back in 2001.

Since it takes 2200 PowerPC 970 chips - aka the G5 - to yield (http://www.theregister.co.uk/content/61/33780.html) just over ten teraflops - much the same as you get from 2000 Athlon 64s (http://www.theregister.co.uk/content/archive/31994.html) - getting similar performance out of just 64 Cell cores is impressive, if Sony and co. can deliver.

Right now, they're just a little way past half way through the five-year Cell research project, so they have a few more years yet to demonstrate the device in action. We'd expect the successors to today's chips to have got a little closer to those kinds of figures by 2006, but not that close.

Others are not so far behind. ClearSpeed's recently announced CS301 chip, for example, can deliver 25 gigaflops peak, the company claims. The CS301 is a 64-way parallel processing co-processor designed to work alongside an x86 or other general purpose CPU. The downside is that it's expected to cost over $1000 per chip. We suspect Sony and IBM are aiming for something a little more mass-market. ®

Reaching back further:

Sony, IBM, Toshiba team on broadband supercomputing CPU

************************************************

The Register » Channel »

Original URL: http://www.theregister.co.uk/2001/03/12/sony_ibm_toshiba_team/

Sony, IBM, Toshiba team on broadband supercomputing CPU

By Tony Smith (tony.smith at theregister.co.uk)

Published Monday 12th March 2001 11:47 GMT

Sony, Toshiba and IBM are to co-operate on what they're calling a "supercomputer on a chip" and which to us sounds like the successor to the Emotion Engine processor currently driving the PlayStation 2.

Codenamed Cell, the new chip will form the basis of a massive $400 million, five-year R&D project. The goal of that research: to create a chip that not only goes like the proverbial off a shovel, but is designed specifically for high speed networks - and multi-processing across them.

Cell will utilise IBM's most up-to-date processor technologies - "copper wires, silicon-on-insulator transistors and low-K dielectric insulation" - all done at 0.1 micron (and probably a lot smaller by the time the thing ships) and fabbed on 12in wafers. It will "deliver teraflops of processing power". A 'flop' is a floating-point maths operation, and one teraflop is one thousand billion flops.

The trio haven't said much more about the chip, other than the tangential references to supercomputer performance and enabling the chip for a world of ubiquitous broadband Net connections. Ultimately, the part will power a wide range of consumer devices.

All that suggests we're looking at a general purpose microprocessor running at high speeds, enabled to process high throughput data streams coming in from all these wide, fast pipelines the partners expect devices containing Cell to be connected to. It's also expected to be a low-power processor. All that sounds like a cross between Emotion Engine, PowerPC and DSPs.

There's an irony here in that IBM fell out with its PowerPC partner Motorola when the latter developed the AltiVec vector processing system to allow the PowerPC to operate as a kind of programmable DSP. That's no use to us, complained IBM, and the two promptly parted ways.

IBM has clearly changed its mind about this kind of thing. It's certainly churning out Motorola-designed AltiVec-enabled PowerPC 7410 CPUs (aka G4) for Apple, and it may also have licensed AltiVec for the PowerPC-based processor it designed for Nintendo's GameCube console, which is due to ship later this year. And given Cell's emphasis on processing broadband-delivered multimedia data, it's not hard to imagine that IBM is working on something very similar to AltiVec for the new chip.

The chip's codename also gives a clue to its functionality. Said Ken Kutaragi, head of Sony's Computer Entertainment division: "With built-in broadband connectivity, microprocessors that currently exist as individual islands will be more closely linked, making a network of systems act more as one, unified 'supersystem'. Just as biological cells in the body unite to form complete physical systems, Cell-based electronic products of all types will form the building blocks of larger systems."

That suggests that multi-processing support is being designed into Cell from day one, doing all sorts of clever stuff like reading any chip's data and instruction caches, NUMA-style - a feature already on Motorola's PowerPC roadmap. And IBM has a keen interest in NUMA, thanks to its purchase of Sequent.

Kutaragi's spiel also implies some degree of clustering too. Again, that's a technology IBM has been poking its nose into a lot of late, allowing it to flog huge Linux-based supercomputing clusters to big name corporate clients.

But before everyone starts getting too excited by all this, here's one other point to note: IBM has been here before. The Sony-IBM-Toshiba alliance is uncannily reminiscent of the Apple-IBM-Motorola alliance. One was formed to create an Intel-busting next-generation computing platform and the other launched the PowerPC.

SIT seems less overtly anti-Wintel than AIM was, the beating-up-on-Intel aspect isn't absent. Kutaragi has talked about beating Intel before.

Whatever, AIM was unable to unseat Intel, and ultimately the partners ended up squabbling and chasing different markets. It's too early to say the same thing will happen to SIT, but five years is a very long time in the computer industry. A lot can - and will - happen between now and Cell's mass production and implementation. ®

From Feb announcement:

Multi-OS Cell CPU tops 4GHz

***********************************************

The Register » Personal » Consoles »

Original URL: http://www.theregister.co.uk/2005/02/08/cell_specifications/

Multi-OS Cell CPU tops 4GHz

By Andrew Orlowski in San Francisco (andrew.orlowski at theregister.co.uk)

Published Tuesday 8th February 2005 03:07 GMT

Technical details of the Cell processor, a joint venture between Sony, IBM and Toshiba, were disclosed in San Francisco today.

But the example chip shown to journalists today is likely to be superseded by faster versions when it appears on the market later this year. The Cell has 234m transistors, measures 221mm² and, as detailed in the patent, has eight execution units, here dubbed "synergistic processors". Cell refers to a piece of software that roams the local machine, a LAN or a WAN looking for execution resources.

<img>

When the unit appears - in enterprise kit from IBM, and in Sony's PlayStation 3 console - it's likely to clock 4.6GHz and be built on a 65nm process. Today's samples used a 90nm process. Cells will be manufactured at IBM's 300mm fab in East Fishkill, New Yorj and Sony's Nagasaki plant.

IBM said the processor is "OS neutral", but it will able to run multiple operating systems concurrently.

Sony and IBM dispelled any doubt that in addition to being suitable for technical and commercial IT, the processor is aimed at the heart of the home: with digital TVs and home servers cited as likely vehicles for the processor.

Many of your comments on the long-term economic and social impact (http://www.theregister.co.uk/2005/02/03/cell_analysis_part_two/) of the processor focus on technical obstacles to its success. We'll round up the best later today. ®

Big money going into this:

Sony to ramp chip spend to $9 billion over three years

The Register » Channel »

Original URL: http://www.theregister.co.uk/2003/05/29/sony_to_ramp_chip_spend/

Sony to ramp chip spend to $9 billion over three years

By Tony Smith (tony.smith at theregister.co.uk)

Published Thursday 29th May 2003 09:24 GMT

Sony plans to spent ¥500 billion ($4.3 billion) over the next three years on chip fabrication facilities and the same figure on chip R&D, the chip giant said yesterday.

This year alone it will spend ¥175 billion ($1.5 billion) on capex and a little less than that on R&D.

Sony has already said it intends to invest ¥200 billion ($1.7 billion) developing a 65nm fab process and building a 300mm wafer plant.

The announcement follows Sony's decision, revealed earlier this month, to combine its various chip development and production operations into a single unit. The new operation is already working on Cell, the next-generation massively parallel processor being co-designed by Sony, IBM and Toshiba. It is also preparing a 90nm version of the PlayStation 2's Emotion Engine CPU which integrates the console's graphics chip on the die.

That part, dubbed the EE+GS@90nm, is the foundation of PSX, the PlayStation 2-based home server Sony announced separately yesterday. The cubic white unit integrates a DVD+/-RW drive, 120GB hard drive, TV tuner and game console. PSX will ship in Japan by the end of the year - giving Sony time to ramp up its 90nm process - and later in 2004 for the US and Europe.

The PSX will ship with an analog TV tuner, though this will ultimately be upgraded to a digital version, Sony said. The product comes from Sony's Broadband Networks Company, and marks the first real convergence product tying in TV, broadband Internet and computing. Microsoft is believed to be working on a similar system as a the next version of its Xbox console. ®

Sony to combine PlayStation and group chip operations (http://www.theregister.co.uk/content/3/30583.html)

From a link in the first article:

*************************************************

IBM Discloses Cell Based Blade Server Board Prototype

May 25, 2005 14:17

The two large packages on the left are the Cell processors.

The prototype used huge heat sinks and cooler fans.

IBM Corp. has revealed a prototype blade server board featuring the Cell microprocessor jointly developed with the Sony Group and Toshiba Corp. The company demonstrated the prototype in front of only a few clients at a hotel room outside Los Angeles, US, at the 2005 Electronic Entertainment Expo (E³), game tradeshow. "We demonstrated the prototype to show that Cell continues to mature. The product is expected to have several times higher performance compared to conventional servers," said an IBM engineer.

The prototype, called the Cell Processor Based Blade Server, measured approximately 23 x 43 cm. Each board featured two Cell processors, two 512 Mb XDR DRAM chips and two South Bridge LSIs. The Cell processors were demonstrated running at 2.4-2.8 GHz. "We are driving the Cell processors at higher rates in the laboratory," said the engineer. "If operated at 3 GHz, Cell's theoretical performance reaches about 200 GFLOPS, which works out to about 400 GFLOPS per board," he added. IBM plans to release a rack product capable of storing seven of these boards.

The Cell processors and South Bridge LSIs on the board were equipped with large heat sinks and cooler fans. Using these components, a rack cannot store seven boards, however, the company expects to store seven boards in a rack by using thin, dedicated heat sinks. The OS used was Linux 2.6.11.

Hiroki Yomogita, Silicon Valley

*********************************************

Blowup of the pictures above:

The two large packages on the left are the Cell processors.

*********************************************

The prototype used huge heat sinks and cooler fans.

Definitions can be tricky:

From : http://search390.techtarget.com/sDefinition/0,,sid10_gci770169,00.html

A blade server is a thin, modular electronic circuit board, containing one, two, or more microprocessors and memory, that is intended for a single, dedicated application (such as serving Web pages) and that can be easily inserted into a space-saving rack with many similar servers. One product offering, for example, makes it possible to install up to 280 blade server modules vertically in multiple racks or rows of a single floor-standing cabinet. Blade servers, which share a common high-speed bus, are designed to create less heat and thus save energy costs as well as space. Large data centers and Internet service providers (ISPs) that host Web sites are among companies most likely to buy blade servers.

A blade server is sometimes referred to as a high-density server and is typically used in a clustering of servers that are dedicated to a single task, such as:

File sharing
Web page serving and caching
SSL encrypting of Web communication
The transcoding of Web page content for smaller displays
Streaming audio and video content

Like most clustering applications, blade servers can also be managed to include load balancing and failover capabilities. A blade server usually comes with an operating system and the application program to which it is dedicated already on the board.

Individual blade servers are usually hot-pluggable and come in various heights, including 5.25 inches (the 3U model), 1.75 inches (1U), and possibly "sub-U" sizes. (A U is a standard measure of vertical height in an equipment cabinet and is equal to 1.75 inches.)

Also see brick server and pizza box server.

Read more about it:

>>	RLX Technologies was one of the first blade server makers.
>>	Nexcom also makes blade servers and describes some applications.

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This word suggested by: Sonia Weaver
Last updated on: Jan 31, 2005

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