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OK - thanks for the "h" version and middle name.

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07/07/05 | #20050149776 | Browse Patent Applications: Prev - Next | Browse Industry: USPTO Class 714
Processing system on an integrated circuit
A processing system on an integrated circuit includes a group of processing cores. A group of dedicated random access memories are severally coupled to one of the group of processing cores or shared among the group. A star bus couples the group of processing cores and random access memories. Additional layer(s) of star bus may couple many such clusters to each other and to an off-chip environment.

Agent: Law Office Of Dale B. Halling - Colorado Springs, CO, US
Inventor: Joel Henry Hinrichs
Class: 714010000 (USPTO), G06F012/00 (Intl Class)

Brief Patent Description - Full Patent Description - Patent Application Claims

RELATED APPLICATIONS

[0001] The present invention claims priority on provisional patent application Ser. No. 60/526,696, filed on Dec. 3, 2003, entitled "CPU".

FIELD OF THE INVENTION

[0002] The present invention relates generally to the field of integrated circuits and more particularly to a processing system on an integrated circuit.

BACKGROUND OF THE INVENTION

[0003] Integrated circuit Central Processing Unit (CPU) architecture has passed a point of diminishing returns. CPUs require greater and greater die surface area for linear increases in clock speed and not necessarily corresponding increases in processed instructions. Present CPUs provide one to three billion instructions per second (1 to 3 GIPS) best case, yet under typical operating conditions these CPUs achieve at most 10% to 20% of their theoretical maximum performance.

[0004] Thus there exists a need for a CPU architecture that requires less die surface area and provides a greater theoretical maximum performance and greater performance under typical operating conditions.

SUMMARY OF THE INVENTION

[0005] A processing system on an integrated circuit that solves these and other problems has a number of processing cores coupled together. A number of random access memories are each dedicated to one of the processing cores. A first group of the processing cores are coupled together by a first star bus. A second group of the processing cores may be coupled together by a second star bus and coupled to the first group of processing cores by a third star bus. One or more shared random access memories may be coupled to the first star bus. The first star bus may be a unidirectional bus. One of the cores is disabled when it tests defective. Additional shared random access memory or memories may be coupled to the second star bus.

[0006] In one embodiment, a processing system on an integrated circuit includes a group of processing cores. A group of dedicated random access memories are each directly coupled to one of the group of processing cores. A star bus couples the group of processing cores. A shared random access memory may be coupled to the star bus. The shared random access memory may consist of multiple independent parts which are interleaved. A second group of processing cores may be coupled together by a second star bus. The second group of processing cores may be coupled to the first group of processing cores by a third star bus. Each of the group of processing cores may have an isolation system. The star bus may be a unidirectional bus.

[0007] In one embodiment, a processing system on an integrated circuit includes a group of processing cores. A star bus couples the group of processing cores together. A group of dedicated random access memories may each be directly coupled one of the group of processing cores. A number of similar groups of processing cores and random access memories, all joined by star buses, may be coupled to the first group of processing cores by a second level of star bus. A shared group of random access memories may be coupled to the second level star bus. The shared random access memories may be interleaved. Each of the group of processing cores may be fusable. Some of the shared random access memories may be fusable.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 is a partial block diagram of a processing system having a multiple cores, each with a dedicated memory, and a plurality of shared memories, on an integrated circuit in accordance with one embodiment of the invention;

[0009] FIG. 2 is a partial block diagram of a processing system having a single core, a dedicated memory, and a plurality of sharable memories, on an integrated circuit in accordance with one embodiment of the invention;

[0010] FIG. 3 is a block diagram of a processing system having multiple cores, each with a private memory, and with a plurality of shared memories, on an integrated circuit in accordance with one embodiment of the invention;

[0011] FIG. 4 is a block diagram of a processing system having multiple groups of multiple cores on an integrated circuit in accordance with one embodiment of the invention;

[0012] FIG. 5 is a block diagram of a processing system for a switch having a group of cores on an integrated circuit in accordance with one embodiment of the invention; and

[0013] FIG. 6 is a block diagram of a processing system for a switch having multiple groups of multiple cores with a central data memory on an integrated circuit in accordance with one embodiment of the invention.

DETAILED DESCRIPTION OF THE DRAWINGS

[0014] The present invention overcomes the limitations present CPU (central processing unit) architectures by having a number or simple processing cores coupled together with small dedicated RAMs (Random Access Memory). This increases the efficiency in the use of die space, since a number of simple cores require significantly less die space for the same theoretical computation power. The use of dedicated local RAM also increases the real computation power of the cluster of processing cores, since the memory access speed is significantly increased. First the memory speed is increased by virtue of the large number of independent RAMs present; and second the memory speed is increased by virtue of the much wider word size available on a die because there is no pin limitation; and third the memory speed is increased by virtue of the fact that very small RAMs have smaller physical distances to traverse hence are inherently faster; and fourth the memory speed is increased by virtue of the fact that there are no chip-to-chip line drivers and no lengthy chip-to-chip signal paths to traverse.

[0015] FIG. 1 is a block diagram of a processing system 10 on an integrated circuit in accordance with one embodiment of the invention. The processing system 10 has a number of processing cores 12. Commonly, each of the processing cores 12 is exactly the same. The processing cores 12 are coupled together usually by a star bus 14. For each processing core 12 there is a dedicated RAM 16 coupled to the processing core 12 by a dedicated bus 18. In another embodiment, many but not all processing cores 12 have dedicated RAMs 16. The processing cores 12 also have access to one or more shared RAMs 20 through the star bus 14.

[0016] FIG. 2 is a partial block diagram of a processing system 30 on an integrated circuit in accordance with one embodiment of the invention. The processing system has a processing core 32. The processing core 32 has a level zero cache 34 and is coupled to a common access port. One embodiment of the common access port is shown, Star Bus 36. The processing core 32 is also coupled through a dedicated bus 38 to a local RAM (Random Access Memory) 40. The common access port 36 is coupled to the local RAM 40 and to one or more shared RAMs 42.

[0017] Note that the processing core 32 (cores 12, FIG. 1) may be simple cores that are generally limited only to those elements which have an immediate practical value. The processing core's 32 instruction set may be generally mapped onto the specific set of machine instructions utilized by C or C++ compilers. This is because computer code that is not written in direct machine language is usually written in C or C++ language. Higher level application languages tend to be embodied in computer code written in C or C++. As a result, this allows the cores 32 (12) to handle most computer programs. The cores may generally not be pipelined and not have specialty instructions for enhancing graphics, text editing or other user-interface matters. In one embodiment, the processing cores are thirty-two bit, single address, CISC cores. These cores may only require 50,000 to 75,000 logic gates.

[0018] The level zero cache is generally very small. It may be as little as one-quarter to one-half kilobytes of live code and data storage.
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