With out a clock their serial flash could never load their algorithm nor could they toggle their flip-flop CLB and output latches. They are so dependent on clocking most contain a digital clock manager (DCM). While this may work with a gate array it simply will not with a FPGA.
They never claimed a clock wasn't part of the FPGA. This is not the clock they are talking about. They are talking about a clock being used when the algorithm is running. The software contains no clock, nor are external clocks used as input.
The paper is found here: http://www.informatics.sussex.ac.uk/users/adrianth/ices98/node1.html
The logic layout (of the final design):
