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Hot Chips conference reflects a changing industry - ( Micro-Processors )
EE Times ^ | July 7, 2003 (3:42 p.m. ET) | Rick Merritt and Ron Wilson

Posted on 07/08/2003 7:52:41 AM PDT by Ernest_at_the_Beach

SAN MATEO, Calif. — The recession's toll notwithstanding, the upcoming 15th annual Hot Chips conference drew a near-record number of paper submissions. But the scheduled lineup shows that Hot Chips, like the industry it examines, has distinctly changed its flavor.

"The focus in design now is on applications and their solutions, not on general-purpose CPUs for everything," said Pradeep Dubey, manager of innovative platform architecture at Intel Corp. (Santa Clara, Calif.) and program co-chairman for the conference, which will convene Aug. 17-19 on the Stanford University campus in Palo Alto, Calif.

Hot Chips traditionally has been a showcase for general-purpose CPU microarchitecture. When clock speed became king in the early 1990s, the conference documented the rise of simplified, pipelined processors that could exploit the rapidly shrinking gate delays of CMOS processes. Later, as CMOS transistor budgets rose faster than logic speeds, Hot Chips papers reported on the emergence of superscalar architectures, branch prediction, speculative execution and threading support.

But all of those advances were documented in the context of general-purpose microprocessors.

''There was a group in the architecture world that felt that if we could make the CPUs fast enough, they could be used for anything,'' Dubey said.

This year's program reflects a different reality. While leading-edge processors-and, now, supercomputers-still incubate architectural ideas, it is the application of the ideas to particular problems that distinguishes the really hot chips.

Reflecting that evolution, the 2003 program of papers will be bookended by sessions on the sources of underlying technology: supercomputers on Monday morning, Aug. 18, and microprocessors on Tuesday afternoon. In between, the floor will be given to application-specific chips.

Monday afternoon sessions will cover embedded processors, graphics processors, a digital NTSC receiver chip and devices for wireless communications. Tuesday will resume the theme with sessions on switching and routing chips, security processors and networking. Tuesday's keynote will examine the future of military microelectronics.

As systems-on-chip have moved beyond single- and even dual-processor configurations to resemble networks-on-chip, work on processor clusters and processor networks in the supercomputing realm has loomed larger in SoC thinking. The Hot Chips meeting will recognize that connection with a session on the interconnect chips that make three of the world's biggest supercomputers possible.

Tadashi Watanabe of NEC Corp. will deliver a keynote describing the company's Whole Earth Simulator, currently ranked as the world's fastest supercomputer (www.top500.org). A representative from Quadrics (Bristol, England) will present a paper on its latest clustering interconnect, developed in conjunction with Los Alamos National Laboratory, presumably for the lab's ASCI Q system, the world's second-fastest supercomputer.

And hardware architect Robert Alverson at Cray Inc. (Seattle) will describe the seven-port router ASIC at the heart of the proposed 10,000-node Red Storm system Cray is building for Sandia National Laboratories. That effort could top the others, at least in terms of raw microprocessor count.

Only seven of the world's top 500 supers use more than 5,000 CPUs; the largest of them is Sandia's existing ASCI Red system, with 9,632 processors. Red Storm will link 10,000 Advanced Micro Devices Opteron CPUs in a 27 x 16 x 24 mesh network, with a single Opteron and Cray ASIC at each node.

That ASIC, built in IBM Corp.'s CU-11 130-nanometer process, is essentially a router with seven ports, each sporting a 3-Gbyte/second aggregate bandwidth based on IBM serial-link technology. The links will carry a proprietary message-passing protocol, managed by a PowerPC core. The interconnects provide error checking at each link and single-hop latency as low as 2 microseconds.

With the ASIC not due back from IBM until the end of the year and no prototype system development starting until early 2004, "it's hard to say if we've learned the big lessons yet," said Alverson.

Key challenges to date have been figuring out how to route around broken links in the mesh and how to anticipate and avoid routes that would lock up the network. One key question is whether the massively parallel-processing (MPP) system will be as efficient as the clustered systems, based on interconnects similar to the one to be detailed by Quadrics, used in many supercomputers today. Quadrics favors a fat-tree topology to the mesh used in Red Storm. But drawing distinctions between the two approaches can be difficult, Alverson said.

"The networking technology we develop will probably be used in subsequent projects here," he said. "We would love to commercialize our work in Red Storm and sell it to others, but a key will be how it compares in cost to clustered systems."

Microprocessors advance


The session on microprocessors will similarly focus on multiprocessing, but on a chip scale. Introductory papers will be delivered on IBM's Power5 architecture, Sun Microsystems Inc.'s Sparc Gemini and two Itanium announcements from Intel. At least the first two architectures include dual-processor chips.

The fourth paper suggests another direction in CPU design-one of equal importance to the rapidly increasing complexity of multiprocessing, multithreading chips. The paper describes a 600-MHz CPU implemented using an accelerated ASIC design flow from fabless ASIC vendor Telairity Semiconductor Inc. The Telairity processor is being offered as a proof point that the difference between ASIC and custom design flows is shrinking and that ASIC flows are already capable of meeting the needs of the whole embedded market.

That thinking marks a striking reversal for the advanced-CPU community, which has always relied on substantial blocks of custom hardware for performance. But it is a mainstream idea in the application-driven embedded world.

''In embedded computing, you still may use custom circuitry, but you use it differently,'' Dubey remarked. ''You may spend a lot of time on an analog or mixed-signal block that will give you a differential advantage. You won't spend that much time on the CPU. For embedded platforms, it's pretty much a case of just picking a CPU and using it. The CPU choice and implementation have very little bearing on the application.''

Dubey pointed in particular to the sessions on wireless communications and on security processors. Those application-driven systems-on-chip typically use an industry-standard CPU core as a control processor. But often the hard work is done in a synthesized data path, and the real differentiation that wins the chip a place in the market comes in either the data-path design or in the integration of custom mixed-signal I/O blocks.

"Perhaps the conference used to be more processor-focused," Dubey said, ''but now we look for 'hot chips' in any area, whether they are general-purpose processors or application-specific embedded designs.''

The advanced program for Hot Chips is at www.hotchips.org.


TOPICS: Business/Economy; Extended News; News/Current Events; Technical
KEYWORDS: computing; computingtrends; microprocessors; techindex

1 posted on 07/08/2003 7:52:41 AM PDT by Ernest_at_the_Beach
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2 posted on 07/08/2003 7:53:38 AM PDT by Ernest_at_the_Beach (Recall Gray Davis and then start on the other Democrats)
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