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Okay. Vector as used by Cray means basically a pipelined system. All parts of the Cray-1 (and subsequent developments along this line) were pipelined. For example, memory latency was 11 clocks and memory cycle type was 4 clocks. By using memory interleaving (the bank address was the least signigicant address bits) one word (64 bits plus parity) could be delivered to the CPU each clock. If addresses were not accessed by multiples of 16 (I think there were 16 banks in the early machines), one got no conflicts. It's like a bucket brigade. The 11 segments from memory to CPU were the latency but the throughput was 1 word per clock.

Other functional units worked the same way. Most units could be "chained" so that one had (on the XMP, YMP series) instructions such as LOAD, LOAD, MULTIPLY (by a scalar) ADD, STORE. Each unit (2 load pipes, multiplier and adder) would be active at the same time, delievering 1 result per clock back to memory. Later Crays had more units and could access memory irregularly (I helped invent this process.)

The last multi-processor Cray I worked on had 2 billion words (16 gigabytes, memory is much cheaper now), 8 processors, where each processor had 2 load pipes, 1 store pipe, and 1 I/O pipe. Memory could be accessed 32 words at a time, irregularly spaced. Of course, the speed of the memory was about 20us so it was like having all cache. (No true cache was used.)