IBM has just announced that its upcoming Power5 CPU will be a multi-core, multithreaded design. The Power5 should theoretically have four times the performance of the Power4, and IBM claims that the Power5's actual performance will be four times as high as Power4's. Power5 will be manufactured on a .13 micron process, and will debut at 1.5GHz or faster. IBM is claiming that samples of the CPU are performing "exactly as we hoped." As impressive as the Power5 appears, there are many unanswered questions regarding this architecture. For instance, how much cache will it have? One can reasonably assume that it will have a hefty on-chip L2 cache, and may come in a multi-chip module with many megabytes of L3 cache. What will the Instructions Per Clock (IPC) of this chip be? What type of a bus will the Power5 have? How will the Power5 partition its resources amongst all the cores and threads? Will IBM eventually introduce a single core desktop CPU based on Power5, just as the 970 CPU is a modified single-chip Power4? If the Power5 is truly four times as fast as the Power4 on real-world applications, that must mean that IBM found a way to keep all of the cores and threads constantly fed with data and instructions.