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Discovery Could Lead To Faster, Smaller, Cheaper Computer Chips
Science Daily | 20 June 2002

Posted on 06/20/2002 11:38:02 AM PDT by sourcery

In a discovery that could greatly reduce the size and cost of computer chips, Princeton researchers have found a fast method for printing ultrasmall patterns in silicon wafers. The method, described in the June 20 issue of Nature, could allow electronics manufacturers to increase the density of transistors on silicon chips by 100-fold while dramatically streamlining the production process. Packing more transistors onto chips is the key to making more powerful computer processors and memory chips.

Researchers in the lab of electrical engineer Stephen Chou used the new technique to make patterns with features measuring 10 nanometers -- 10 millionths of millimeter. The method involves pressing a mold against a piece of silicon and applying a laser pulse for just 20 billionths of a second. The surface of the silicon briefly melts and resolidifies around the mold.

The method eliminates the costly and time-consuming step of etching, or photolithography, which had been the only way to make such small patterns in silicon. While the etching process takes 10 or 20 minutes to make a single chip, Chou's imprint method accomplishes it in a quarter of a millionth of a second.

"Here you do not need to use all those steps," said Chou. "You just imprint the pattern directly into the silicon. You not only reduce the number of steps, you can do it in nanoseconds."

Chou's co-authors on the paper are graduate students Chris Keimel and Jian Gu.

In a commentary accompanying the research report in Nature, electrical engineer Fabian Pease of Stanford University wrote that the new method could allow electronics manufacturers to continue the rapid pace of miniaturization that has continued for three decades, but appeared to be running up against fundamental physical limits.

Chou has made a career of breaking what had appeared to be physical limits of miniaturization. In 1996, he developed a method for imprinting nanometer-scale patterns into plastic polymers. That breakthrough greatly simplified the process of making molds, but costly etching was still required to transfer these patterns into silicon.

Chou believed that imprinting would work directly in silicon and could be made to happen much faster.

"People's intuition is that mechanical processes are very slow, so imprinting cannot be fast," said Chou. "But I knew there is no scientific proof of that. So how do you design an experiment to explore the speed limit of the imprint process?"

The key turned out to be a tool called an excimer laser, which is commonly used in laser surgeries because it can heat just the thinnest surface layer of a material without causing damage underneath. Using conventional etching, Chou made a template of the pattern he wanted out of quartz, which is transparent to the laser beam, and pressed it against the silicon. A brief laser pulse melted the silicon surface around the mold. The silicon does not stick to the quartz.

Revealed by electron microscopes, the patterns the researchers produced look like long, squared-off channels. Each ridge measures 140 nanometers across and is topped by a much smaller ridge just 10 nanometers wide. By comparison, a 10-nanometer ribbon next to a human hair would look like the lead of a mechanical pencil next to a train car.

Chou dubbed the method Laser-Assisted Direct Imprint, or LADI. The University has submitted an invention disclosure, which initiates the process of filing for a patent. He believes the LADI process will mesh well with another of his earlier breakthroughs, his creation in 1996 of the world's smallest transistor, which requires only a single electron of current. Making common use of such small transistor has been inhibited by lack of a convenient manufacturing process, he said.

Another benefit of LADI, said Chou, is that it eliminates the chemicals used in conventional lithography and is thus more environmentally friendly.

In addition to its commercial applications, the discovery opens an interesting avenue of scientific research, said Chou. Understanding the physics behind melting and solidifying on such small scales will require input from many fields, including materials science, mechanics and microfluidics.

"Scientifically, people are still trying to understand how it works, because it is amazing that it works at all," said Chou.

Editor's Note: The original news release can be found at http://www.princeton.edu/pr/news/02/q2/0619-ladi.htm


TOPICS: Miscellaneous; Technical
KEYWORDS: techindex

1 posted on 06/20/2002 11:38:02 AM PDT by sourcery
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To: Ernest_at_the_Beach; Libertarianize the GOP
FYI
2 posted on 06/20/2002 11:38:36 AM PDT by sourcery
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To: sourcery
Current silicon processes are around .13 microns (or 130 nanometers, billionths of a meter) for the transistor length and about 200-250 nanometers for the wire widths and spacing, usually drawn on a grid of .01 microns, or 10 nanometers. This is talking about features being drawn at 10 nanometers, presumably on a grid defined in Angstroms (.1 nanometers, probably defined at 5 Angstroms per grid step).

Holy Ned! My head is spinning. I've worked in the semiconductor industry for over twenty years, I remember when processes were "5 and 5", or five micron wires with five micron spacing. To think that there is serious progress being made with designs being etched with Angstrom resolution. Wow. Of course, it will be years before this is implemented, if ever.

3 posted on 06/20/2002 11:51:33 AM PDT by Billy_bob_bob
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To: sourcery
My question is, with devices this small, will random radiation such as cosmic rays act upon the devices to produce calculation errors?
4 posted on 06/20/2002 11:58:10 AM PDT by RLK
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To: sourcery; *tech_index; Mathlete; Apple Pan Dowdy; grundle; beckett; billorites; ErnBatavia; ...
Thanks for the ping!

To find all articles tagged or indexed using tech_index

Click here: tech_index

5 posted on 06/20/2002 12:17:04 PM PDT by Ernest_at_the_Beach
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To: RLK
That's what checksums are for. The answer to your question is that there are levels of redundancy built in the architectures, so random errors that happen in calculation or data transmission are caught and tossed out. FYI.
6 posted on 06/20/2002 12:17:55 PM PDT by Billy_bob_bob
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To: Ernest_at_the_Beach
thanks for the ping
7 posted on 06/20/2002 12:21:19 PM PDT by Fish out of Water
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To: sourcery
COOL. Just to think pretty soon the chips will just make themselves.
8 posted on 06/20/2002 12:21:37 PM PDT by OXENinFLA
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To: Billy_bob_bob
Did you see this?

IBM nanotechnology creates 1-terabit memory

It would be interesting to see your comments on the processes used there compared to those in this article.

It is tough for a novice to grasp the significance of some of these articles.

9 posted on 06/20/2002 12:24:08 PM PDT by Ernest_at_the_Beach
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To: Ernest_at_the_Beach
I found it interesting that two of the researchers are Chinese. Is that a reflection of the premise that most good engineering schools have a majority of Asians in school vs. few caucasians? Inquiring minds want to know...
10 posted on 06/20/2002 12:33:08 PM PDT by Paulus Invictus
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To: sourcery
Texe Marrs gonna have a field day with this!
11 posted on 06/20/2002 12:33:42 PM PDT by JmyBryan
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To: Ernest_at_the_Beach
The process they are describing is wholly different from current technology. The new IBM memory technology is using nanomechanical moving parts to actually punch holes in a polymer substrate, which can apparently be "healed" somehow. Hole = 1, no hole = 0, now you have your memory. I imagine the final product will end up being superceded by advances in silicon technology. Never underestimate the advantage in upgrading current infrastructure. I remember seeing charts in the 80's that said that CMOS would be dead by 1992. Well, the CMOS process boys didn't see that chart, since about %85 of all of the chips in the world made today are CMOS.

Still, the technology IBM is working on is great stuff, and will most likely pay off in unexpected ways. Nanotech will be a powerhouse technology in twenty years, producing as much wealth and employing as many people as electronics does today, mark my words.

The technology that I find most exciting is what is being done with "polymer" transistors. The possibilities presented by this technology are astonishing. Imagine a factory that makes PDA's, or cell phones or home computers. Imagine this factory taking in no components of any kind, instead the loading dock takes in only sheets of plastic and barrels of various polymers. Imagine the plastic having layer upon layer of polymers sprayed upon it, forming everything from recesses to place batteries into, to power supplies, to CPU's and displays and buttons and everything in-between. Imagine a wall sized TV that comes in a tube, and you unroll it on your wall like it was an old Grateful Dead poster. Imagine windows that have solar cells built in, or built in darkening on command, made almost as cheaply as regular windows are now. After all, this "polymer transistor" technology is basically a glorification of ink-jet printing.

12 posted on 06/20/2002 12:38:11 PM PDT by Billy_bob_bob
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To: Billy_bob_bob
I am trying to remember whether we have seen anything posted about that here on the Tech_Index list.

If you see some decent readable articles we ought to post a few.

That sounds like it would be a powerful technology!

13 posted on 06/20/2002 3:11:53 PM PDT by Ernest_at_the_Beach
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To: sourcery
Not to be a cynic, but if I had a buck for every press release or news report that claimed some new discovery leading to "Faster, cheaper computer chips", I'd be a fairly wealthy man.
14 posted on 06/20/2002 3:13:35 PM PDT by fogarty
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To: sourcery
Thanks for the ping
15 posted on 06/20/2002 5:48:37 PM PDT by Libertarianize the GOP
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