I kind of thought your reply was intended that way. But I'm not very clued-in to the way these threads work sometimes, so I wasn't entirely sure.
Thanks GSH
I have replied to you and pointed out you misunderstood the information. Nothing you said was incorrect, but you misread the claim that the design did not use a clock for a claim tha the FPGA had no clock.
The claim that the design used no clock is because it exploits asynchronous logic. Unlike synchronous logic, no clock is used to control state changes.