AMD cuts Opteron prices by up to 35%

The Register ^ | 29/07/2003 at 14:45 GMT | Tony Smith

[Ernest_at_the_Beach]

Starting to get interesting!

[Ernest_at_the_Beach]

OFFICIAL BUMP(TOPIC)LIST

[krb]

Any word on how much work is necessary to recompile code for these new 64 bit architectures?

I would really, really love video editing software that could be make to fly on these things.

[krb]

Any word on how much work is necessary to recompile code for these new 64 bit architectures?

I would really, really love video editing software that could be make to fly on these things.

[lelio]

Supposedly you can get a CVS version of GCC that can generate AMD64 code, but I haven't looked into it.

[krb]

Cool...

[Elliott Jackalope]

As I understand it, recompiling software for these new processors is not difficult, and they are also designed to handle 32-bit code in a native mode. However, these new 64-bit designs don't bring much in the way of additional computational horsepower to the table, they bring the ability to handle extremely large files to the table, like tens of gigabytes of RAM. That in itself is very cool if you are into video.

I'm going to go out on a limb here and say that, (again, as I understand it) the only way that future processors are going to be able to take advantage of wider word lengths is going to involve a different architecture from the ones being used today, neither CISC or RISC but something more like VLIW (Very Long Instruction Word). VLIW makes it possible to handle multiple instructions in one clock cycle. Current architectures cannot do that, and how many bits does it take to contain a "fetch" command, or a "multiply" operator?

[Ernest_at_the_Beach]

VLIW is the Itanium structure is it not?

Means you have to recompile and likely recode everything!

[Ernest_at_the_Beach]

Couple of mother boards reviewed :

2P Opteron Motherboards: Tyan and MSI

[Elliott Jackalope]

Yes, and yes. However, the Itanium is not doing well in the marketplace. Lack of backward compatability seems to be the biggest problem.

[Only1choice____Freedom]

Cool! I can finish my son's computer now!
His chip is now affordable.

[krb]

VLIW makes it possible to handle multiple instructions in one clock cycle.

That's if you have the compiler support to detect and take advantage of instruction-level parallelism.

Current architectures cannot do that,

That is not totally true. There are other schemes that achieve IPC (instructions per clock cycle) greater than 1 on super-scalar architectures. The DEC Alpha is a good example, as well as the PowerPC.

I personally think that multi-threaded architectures are the way advancement is going to be made.

[Grampa Dave]

What does the XP stand for re some of the AMD chips, like, "DTR* Athlon XP-M 2800+"?

[Ernest_at_the_Beach]

What are you building?

[Ernest_at_the_Beach]

The table of the XP processors price changes are just for the MP Models! The DR and LV is new to me, and must tie back to the more popular terminology of Palomino, Thoroughbred and Barton but I am not quite sure !

I am not even sure that there was a Barton MP model produced!

[kitchen]

Here's a site with weekly CPU price checks. Should see a change on next week's update.

[dogbyte12]

In 15 years we will be bitching about 64 bit processors, I just know it.

Then we wil get our new 4 Terahertz processors with 80 TB of RAM, running 128 bit software and begin to bitch about that.

[Grampa Dave]

Thanks. After a week of fighting to correct my XP, I wondered if XP meant the chip had XP codes in it.

[Ernest_at_the_Beach]

OK , what chip do you have in your lovely box?

[Grampa Dave]

I have a Pentium 4, rated at 1.8.