[Dr. Sivana]

There are old single core chips with 184 million tranistors (Pentium 4), and six core i7 chips with close to 2 billion. The 621 million transistor count sounds low for a 1000 core chip. We used to worry about the overhead of managing that many cores. Has that problem been solved?

[HiTech RedNeck]

Sounds like a relatively simple core.

[Darth Reardon]

Perhaps that says more about what we have today being bloated.

This thing has a 72 count instruction set. That’s less than the 8086 started with.

[Edward.Fish]

There are old single core chips with 184 million tranistors (Pentium 4), and six core i7 chips with close to 2 billion. The 621 million transistor count sounds low for a 1000 core chip. We used to worry about the overhead of managing that many cores. Has that problem been solved?

The low transistor count is from this: each of the seven-stage-pipelined cores has a 72-instruction set, single instruction/cycle.
I think the best thing to do WRT managing that many cores is to treat them as a resource (like memory) and apply management/scheduling to them... it'd probably help to have several reserved for OS usage (rather like the registers on [IIRC] MIPS machines).

[ronnietherocket3]

There are old single core chips with 184 million tranistors (Pentium 4), and six core i7 chips with close to 2 billion. The 621 million transistor count sounds low for a 1000 core chip. We used to worry about the overhead of managing that many cores. Has that problem been solved?

Based on low power consumption, and only having 72ops, I am guessing that they skipped branch prediction, floating point units, special function units, vector processing units and a large number of other things that are virtually necessary on a modern CPU or GPU.

They did good work here and their research will probably bear fruit in the 10-20 year timeframe. It may be interesting if some of the cores were general purpose and others were algorithm specific and a hardware scheduler could look ahead a few thousand ops and assign to a processor based on the operations being executed. For example, some applications run lots of threads were some of the threads handle sockets and comms and other threads are heavy on math. By specially designing cores throughput could go up with out having lots of useless transistors leaking current.